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Magillem Connectivity

A complete SoC integration solution to accelerate complex system design

Magillem Connectivity

Overview

Automate SoC assembly and focus on innovation

For design teams coping with exploding complexity and the need to innovate quickly, the Magillem® 5 Connectivity product streamlines and shortens the integration process by 30% to create correct-by-construction platforms.

By accelerating IP deployment with continuous integration, Magillem Connectivity delivers a powerful automated hardware development flow adapting to changes and eliminating time spent on tedious tasks to focus on what matters most.

Reduce large-scale SoC designs integration from months to weeks

With a proven data model based on the IP-XACT industry standard, Magillem Connectivity enables:

IP packaging for the efficient handling of all aspects of system integration for connectivity and configurability.
Automatic IP instantiation and error-free connection process with a solid API to access all the design data.

Magillem 5 Connectivity allows a significant jump in productivity, predictability with progress reporting, and portability of the design environment. For very large designs with thousands of instances, it streamlines the integration process and helps decrease design cycle time by up to 30%.

Restructure for an Error-Free Design to Meet Power and Floorplanning Constraints

Meet power and floorplan constraints with error-free design restructuring

Magillem Connectivity helps eliminate painful, manual steps across the build flow and optimize the time-consuming physical design netlist. It delivers automated hierarchy manipulation capabilities with built-in checks ensuring high-quality generated design.

Separate RTL hierarchy and physical hierarchy enables powerful features, including feedthrough connections for abutted floorplan and hard macros replication.
Rapid response to physical design requirements, reducing the process from weeks to 1 to 2 days.
Drastic improvement in development time and SoC quality through continuous integration flow.

Generate error-free system maps

Full integration of Magillem Registers and Magillem Connectivity helps synchronize connectivity and memory map information:

Calculate and display the system map from the selected initiator.
Confirm that memory regions defined in the memory map can be reached (presence of a physical path).
Check that all the software visible elements (registers or memory regions) in connected targets are present in the memory map.

Error-Free System Map Generation

Magillem Connectivity Key Features

Project management: Design navigation and data aggregation.
Parameters configuration: Hierarchical propagation or overriding.
SoC assembly: Bus i/f detection, rule-based connectivity, bus/signal split/tie/open, hierarchical connection, glue logic insertion, feedthrough.
Hierarchy manipulations: Move, merge, and flatten a physical/virtual hierarchy for RTL restructuring/partitioning.
Platform derivatives: With the incremental design, automatic update, and design diff and merge capability.
Comprehensive checkers: Catch errors as you enter the design information before running any simulation.
Advanced generation capability: RTL netlist generation, in addition to makefile scripts for an extensive range of EDA tools
Tool integration: Tight link with the connectivity tool to generate a system address map when both tools are combined.

Explore additional Magillem Connectivity features, download the datasheet.

Full NoC integration for automated flow

Leverage SoC connectivity information:

Increase productivity with reduced process.
Improve quality with early error detection by checkers.

NoC Integration Automated Flow

Magillem Connectivity product benefits

True IP reuse methodology

Vendor-independent IP packaging (IP-XACT based) simplifies IP reuse across systems.

Shorten and streamline integration

Automated processes help accelerate connectivity.

Continuous integration

The robust SoC build process adapts safely and quickly to changes.

Single source of truth

Consistency and interoperability between the design flow steps are made possible in a unified environment.

Correct by construction

Built-in checkers ensure high-quality designs.

Reduce effort and rework

Automation helps ensure repeatability and eliminate human error.

Leverage technical expertise

Arteris technology helps reduce repetitive and time-consuming tasks so developers can focus on core business innovation.

Boost productivity

Automatic design flow achieves consistent high-quality design and reduces time to market.

Magillem Platform

Powerful comprehensive SoC integration automation

Category	Features	Magillem Packaging	Magillem Connectivity	Magillem Registers
IP-XACT Conversion	2009 to 2022
IP-XACT Conversion	2014 to 2022
Resource Management	Projects
	Catalogs
	Components
TGI	TGI API
HDL Import	Verilog/SystemVerilog support
HDL Import	View & FileSet elaboration
Bus Interface	Auto mapping
Rules Checkers	Design and component
	Memory and system map
	Configurable checker severity
Assembly	Rule-based connectivity
	Bus/signal split/tie/open/feedthrough
	Glue logic insertion
RTL Netlist Generation	Configurable header
	Keep parameter expressions
	Signals/netname/tie management
Hierarchical Manipulations	Merge, Flatten, Move operations
Hierarchical Manipulations	Parameter propagation
IP Update	Rename/resize/delete/merge
IP Update	User mapping rules definition
Diff and Merge	Accept/Reject any change
Diff and Merge	Conflict resolution wizard
Import Memory Map Description	SystemRDL support
	IP-XACT support
	Excel spreadsheets support
Generate HSI Outputs	RTL register bank (VHDL, Verilog, SystemVerilog)
	Customized C Header files
	UVM RAL files
	Documentation (Word, FrameMaker, HTML)
	SystemRDL description
	IP-XACT description

Product Options

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Architectural: UPF- Based Power Flow

Produce UPF script file
Produce diagram based on domain hierarchies
Powerful checks detecting early any issue or inconsistency between RTL and power intent

Customer Testimonials

Trusted by innovative
 companies everywhere

Reliable and fast design capture: tedious tasks are hidden for the SoC integrator.

Using Arteris FlexNoC allows us to reduce development time and manage project risk. FlexNoC’s advanced quality-of-service and debugging features, combined with its multi-protocol support, allow Samsung SUHD TVs to reduce power consumption and die area for complex chips with more than 100 IP interfaces.

Reliable and fast design capture: tedious tasks are hidden for the SoC integrator.

Our successful adoption of Arteris FlexNoC fabric IP has been straightforward, allowing us to more quickly architect and implement sophisticated systems-on-chip in less time and with better power consumption and performance.

Resources

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Datasheets

Magillem Connectivity Datasheet – Complete SoC Integration Solution

Infographics

Simplifying SoC Integration with Arteris

Podcasts

Presentations

Solution Briefs

Accelerate and Optimize AI-Based SoC Designs with Arteris

Videos

Webinars

Accelerate Time To Market With a First-Time Right Process

White Papers

White Paper

Making SoC Integration Simple – Achieve Higher Productivity and Quality

This paper explores engineers’ challenges, how Arteris can help, and why such solutions will not only benefit design teams in the short run by boosting their productivity and achieving successful tape-outs but will also result in long-term savings as the teams are free to focus on the core business and leverage their technical expertise where it matters most.

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Flexible design scalability
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Built on silicon-proven NoC IP and Magillem™ automation to scale modular architectures, simplify multi-die projects, and compress development schedules.