Case Studies

Title Summary
Shortening Leading-Edge ADAS Design Cycles With FlexNoC To Deliver Customer Success Sondrel delivered implementation-ready RTL based on client concepts reducing design time from 4-5 months down to 1-2 months on advanced ADAS SoC designs using Arteris IP.

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Datasheets

Title Summary
SoC & Hardware / Software Interface (HSI) Development Datasheet
  • Productivity: Get all product teams on the same development platform. Replace ad-hoc scripts, local know-how, empower true innovation
  • Manage risk: Reliable scalability for larger designs, derivatives demanding a shorter schedule. Follow industry leaders in mobile, automotive, others
  • Collaboration: Easily collaborate with other design teams and partners
Arteris® Harmony Trace™ Datasheet
  • Increases system quality and functional safety assessments by identifying and fixing the traceability gaps between disparate systems
  • Unique because it gives engineers the freedom to use the “best tool for the job” and automates linking requirements and artifacts
  • Implemented as an enterprise-level server-based application with a web-based user interface (UI)
Product Information Management Datasheet
  • Provide partners datasheets in real-time: Generate key parametric documentation at any time from in-process designs
  • Quality: Ensure all documentation & specifications are fully in sync with latest updates to the design
  • Compatibility: Standard formats are easily integrated with Tech Pubs systems
FlexNoC® Datasheet
  • Non-coherent network-on-chip (NoC) interconnect IP
  • Protocol interoperability: AMBA AXI, AHB, APB, OCP, PIF; custom / proprietary
  • Reduce wire routing congestion, die area & power consumption
  • Meets ISO 26262 ASIL D requirements
FlexNoC® Resilience Package Datasheet
  • Adds safety mechanisms to FlexNoC IP
  • ECC, hardware unit duplication
  • Adds safety controller
  • Adds FMEDA output
FlexNoC® AI Package Datasheet
  • Mesh, ring and torus topology generation and editing
  • Efficient multicast and broadcast
  • VC-Link™ virtual channels; Source synchronous communications
  • HBM2 support
  • Optional Resilience Package to meet ISO 26262 ASIL D functional safety requirements
  • Optional PIANO Timing Closure Package to automate timing closure with floorplan information
Ncore® Datasheet
  • Cache coherent network-on-chip (NoC) interconnect IP
  • Arm® AMBA® CHI and ACE interoperability; CCIX protocol support for multi-chip systems
  • ISO 26262-compliant functional safety mechanisms
CodaCache™ Datasheet
  • Standalone, highly configurable last level cache
  • Arm® AMBA® AXI compliant
  • Configurable way partitioning, sizing, & scratchpad configurations

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Presentations

Title Summary
Architecting the Future of Deep Learning Presentation Learn about the history of artificial intelligence (AI), machine learning, (ML), and deep learning. Keynote presentation at the 2018 eSilicon "ASICs Unlock Deep Learning Innovation" seminar.
KEYWORDS: Artificial intelligence (AI); machine learning (ML); neural networks (NN); deep learning
Arm TechCon: Implementing ISO 26262 Compliant AI System-on-Chip with Arm and Arteris IP Arm, Arteris IP, and Dream Chip Technologies joint presentation from Arm TechCon 2019 explains IP integration requirements for AI subsystems in ISO 26262-compliant chips. With an emphasis on techniques and safety mechanisms to enhance the diagnostic coverage of SoCs integrating an NPU and Safety Island. Topic areas include system design to comply with ISO 26262, system-level diagnostics, Network-on-Chip (NoC) safety mechanisms, subsystem isolation, and end-to-end error protection.
KEYWORDS: ISO 26262, functional safety, automotive, neural network
Arm & Arteris IP AI and ISO 26262 Presentation Arm & Arteris IP joint presentation from ICCAD China 2018 describes how new artificial (AI) and machine learning (ML) acceleration IP from Arm, like the Arm(R) NPU and Mali (TM) C71, can be implemented in ISO 26262-compliant automotive systems with the help of functional safety mechanisms in the Arteris IP FlexNoC and Ncore interconnects.
KEYWORDS: IOS 26262, functional safety, automotive, neural network
Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs) Presented at IQPC Application of ISO 26262 2022 Conference, describes an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics at a level that scales with the size and complexity of an SoC and enables reuse for the creation of SoC platform derivative chips, which is common in our industry.
KEYWORDS: FMEDA, traceability, functional safety, ISO 26262
Challenges Adopting Fault Injection to Support Safety Analysis in Complex SoCs Learn about fault simulator and EDA tools requirements; Using FMEA to create fault injection campaign; Guidelines/lesson learned for simulating different fault types; Analysis and documentation.
KEYWORDS: ISO 26262, SoCs, FMEA, fault, safety
FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs) Failure modes, effects, and diagnostic analysis (FMEDA) for sophisticated chips with hundreds of IP blocks are fraught with complexity and opportunities for systematic errors. This presentation will describe an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics.
KEYWORDS: FMEDA, traceability, functional safety, ISO 26262
Fundamentals of ISO 26262 Part 11 for Semiconductors Arm TechCon presentation that describes what is new in ISO 26262 2nd Edition Part 11, "Guidelines on application of ISO 26262 to semiconductors."
KEYWORDS: ISO 26262; diagnostic coverage; FMEDA; and ASIL tailoring
Implementing Low-Power AI SoCs Using NoC Interconnect Technology Presented at The Linley Spring Processor Conference 2020, describes lessons learned using network-on-chip (NoC) technology to implement AI processing SoCs that meet explosive bandwidth and tight latency requirements while meeting stringent power consumption needs.
KEYWORDS: AI/ML, neural network, low power
Implementing Machine Learning & Neural Network Chip Architectures Presentation describes types processing elements for neural net acceleration, current state-of-the-art AI SoC architectures, and influence of interconnect and memory architectures on AI data flow.
KEYWORDS: Artificial intelligence (AI); machine learning (ML); neural networks (NN); hardware acceleration
Lessons Learned Integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip Presented at the ISO 26262 for Semiconductors (Munich) Conference, this presentation describes the differences between "regular" and AI-enabled automotive chips in the following dimensions: PPA, Safety and Schedule.
KEYWORDS: ISO 26262, AI/ML, functional safety, fault injection, neural network
Is the Missing Safety Ingredient in Automotive AI Traceability? Presented at The Linley Spring Processor Conference 2022, describes the importance of traceability as it applies to managing SoC requirements and customer deliverables whilst also shortening the path to functional safety certification including ISO 26262.
KEYWORDS: traceability, AI/ML, functional safety, ISO 26262, ADAS.
ISO 26262: FMEA before FMEDA This Automotive IQ "Guidance of ISO 26262 to Semiconductors" presentation includes, develop, plan analyze, merge, and validate failure mode effects (FMEA) creation flow. IP architecture and best practices, examples of element decomposition, and merging element analysis and much more.
KEYWORDS: ISO 26262, FMEA, FMEDA, safety mechanisms, fault injection
ISO 26262: System-on-Chip (SoC) Safety Analysis for ADAS and AV Training materials for the 3-hour workshop at the Automotive IQ 8th Annual ISO 26262 for Conference in Dusseldorf, Germany. Explains how explains how SoC integrators validate FMEDA metrics using fault simulators and EDA simulations, and how system design teams can take advantage of these results to optimize the system-level safety concept.
KEYWORDS: ISO 26262; FMEDA; fault injection
ISO 26262: What to Expect from your Chip or IP Provider This Automotive IQ "Guidance of ISO 26262 to Semiconductors" presentation provides "lessons learned" regarding ISO 26262 deliverables that Tier-1s and semiconductor vendors should expect from their suppliers along with practical advice given regarding the DIA and Safety Manual contents as well as FMEDA expectations for configurable IP.
KEYWORDS: ISO 26262, FMEDA, FMEA
Routing Congestion: The Growing Cost of Wires Arm TechCon presentation that describes the benefits of benefits of packet-based on-chip interconnect networks.
KEYWORDS: network-on-chip (NoC); routing congestion
Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP Principles and real-world practices of ISO 26262 for semiconductor design teams. Explains how configuration in IP design can be used as an advantage to automatically drive fault injection using Synopsys Z01X tools. We will demonstrate using a real case study of diagnostic coverage, FMEDA creation and ASIL determination for a fully configurable IP.
KEYWORDS: Synopsys Z01X; fault injection; FMEDA; ASIL

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Technical Papers

Title Summary
A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation.
KEYWORDS: Network-on-Chip (NoC); Routing congestion; physical design
A Design Flow for Critical Embedded Systems In this paper by Airbus, Thales, STMicroelectronics, Arteris IP and other, learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems.
KEYWORDS: DO-178C, DO-254, ARP4754, ECSS Q60-02, Q80, E40, High-Level Synthesis, SystemC/TLM, IP-XACT, Assertion-Based Verification (ABV), Property Specification Language (PSL)
A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis This paper presents a lightweight and cost-effective approach to power estimation suitable for software developers. It relies on trace analysis and high-level modeling of architectures to perform quick and efficient power consumption estimations without losing accuracy.
KEYWORDS: power consumption; embedded software design; power management; trace analysis
A SystemC Extension for Enabling Tighter Integration of IP-XACT Platforms with Virtual Prototypes This paper describes a configurable SystemC extension that simplifies the syntax for expressing register and bitfield accesses and enables automation of virtual platform and hardware-software interface (HSI) development.
KEYWORDS: SystemC, Virtual Hardware Prototyping, IP-XACT, code generation
AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases This 12-page paper published in the peer-reviewed IEEE Design & Test journal explains how Universal Verification Methodology (UVM), initially developed for digital systems, can be extended to analog and mixed signal systems with the help if IP-XACT-based IP packaging and design flow automation.
KEYWORDS: Coverage Driven Verification (CDV), Design Under Test (DUT), Electronic Control Unit (ECU), Electronic System Level (ESL), functional verification, Hardware In the Loop (HIL), system simulation, SystemC, SystemC-AMS, Timed Data Flow (TDF), Transaction Level Modeling (TLM), Universal Verification Methodology (UVM), system verification, Virtual Prototyping (VP)
Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC Peer-reviewed technical journal article from Springer's "Design Automation for Embedded Systems Journal." Summarizes the various features a NoC is required to implement to be integrated in modern SoCs. Describes a top-down approach, based on the progressive refinement of the NoC description from its functional specification (Sect. 4) to its verification (Sect. 8).
KEYWORDS: Network-on-Chip (NoC); Quality-of-Service (QoS); Routing
Building a Portable Stimulus Flow Based on Magillem IP-XACT Packaging This paper written by Nokia and Mentor Siemens describes an efficient integration flow using Portable Stimulus and IP-XACT flow automation.
KEYWORDS: IP-XACT, portable stimulus, verification intent, design under test (DUT)
CodaCache: Helping to Break the Memory Wall This paper describes a novel configurable last level cache IP, CodaCache, that provides an easy-to-integrate solution giving system architects the capability to configure and adapt to their specific needs. Key technologies implemented in this IP are per-master way partitioning, scratchpad RAM allocation, AXI interfaces and functional safety mechanisms.
Easing Heterogeneous Cache Coherent SoC Design using Arteris’ Ncore Interconnect From The Linley Group, publisher of Microprocessor Report. 9-page paper explains new hardware interconnect IP technology that enables cache coherent communication between different types of compute engines in and SoC.
KEYWORDS: Cache coherence; Proxy cache; Network-on-Chip (NoC);
Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product Written by an ISO 26262 working group member who contributed to the new ISO 26262:2018 Part 11, this paper dispels myths about ISO 26262 certification and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.
KEYWORDS: ISO 26262 certification; ASIL; FMEDA
Generation of UVM Compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS This paper presents a methodology and flow to automate the test bench creation for automotive heterogeneous HW/SW systems, using SystemC, SystemC-AMS and IP-XACT.
KEYWORDS: Simulation; Verification; EDA Automation; SystemC; SystemC-AMS; IP-XACT; UVM
How to Efficiently Achieve ASIL-D Compliance Using NoC Technology A closer look at ASIL-D compliance options for on-chip interconnects and NoCs, including redundancy, path diversity and error correction codes (ECC) is required to fully optimize an on-chip network to meet rapidly evolving technology and customer demands.
KEYWORDS: Network-on-chip (NoC); ISO 26262; functional safety; redundancy; ECC
HW / SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures This paper presents a code generation flow to deploy system applications over hardware architectures based on abstract descriptions.
KEYWORDS: HW/SW Interface, IP-XACT, hardware abstraction layer (HAL)
Optimizing Enterprise-Class SSD Host Controller Design with Arteris FlexNoC Network-On-Chip Interconnect IP Enterprise SSD Endurance & Data Protection technical paper that explains how the leading enterprise SSD controller design teams are using network-on-chip (NoC) interconnect technology to optimize their designs for power consumption and performance while increasing reliability and availability.
KEYWORDS: Network-on-chip (NoC); routing congestion; SSD
Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding An oldie but a goodie: Explains power benefits of NoC technology by characterizing a multi-processor system-on-chip (MPSoC) for MPEG4, AVC/H.264 encoding. Explains NoC power model used to analyze power consumption and dissipation.
KEYWORDS: Network-on-chip (NoC); power consumption
Re-Architecting SoCs for the AI Era This paper defines AI, describe its applications, the problems it presents, and how chip designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design.It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.
KEYWORDS: Artificial Intelligence (AI), Machine Learning (ML), Dataflow, ISO 26262, Functional Safety, Semiconductor
Reinventing Traceability: Adding Domain Intelligence with Arteris Harmony Trace™ This paper proposes and explains the Arteris Harmony Trace solution which Increases system quality and functional safety assessments by identifying and fixing the traceability gaps between disparate systems.
KEYWORDS: Traceability; IP-XACT; Requirements; EDA Automation; Functional Safety; Quality; ISO 26262; IEC 61508; ISO 9001; IATF 16949
Routing Congestion: The Growing Cost of Wires The congestion of wires in the place and route (P&R) stage of chip design poses an increasingly significant challenge to creating low cost, high performance chip designs. This paper introduces packet based network-on-chip as a means of enabling configuration link widths, shows experimental results, and describes other benefits of packet-based interconnect networks.
KEYWORDS: Network-on-Chip (NoC); Routing congestion; physical design
Scalability - A Looming Problem in Safety Analysis Misbehavior in the electronics can lead to accidents, even fatalities. This paper describes how ISO 26262 standard and in particular the Failure Modes, Effects and Diagnostic Analysis (FMEDA) can be leveraged to address this real concern.
KEYWORDS: FMEDA; ISO 26262; Traceability; IEEE P2851
Using Machine Learning for Characterization of NoC Components This Award Winning Paper was presented at Synopsys SNUG Silicon Valley 2019. You will learn about modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters. PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized.
KEYWORDS: ML, PPA,
Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP Principles and real-world practices of ISO 26262 for semiconductor design teams. Explains how configuration in IP design can be used as an advantage to automatically drive fault injection using Synopsys Z01X tools. We will demonstrate using a real case study of diagnostic coverage, FMEDA creation and ASIL determination for a fully configurable IP.
KEYWORDS: Synopsys Z01X; fault injection; FMEDA; ASIL; ISO 26262
Using Virtual Prototypes to Improve the Traceability of Critical Embedded Systems Flow This paper written with Imperas explains how the combination of innovative traceability techniques with an advanced virtual prototyping execution environment helps to detect and locate critical embedded system bugs situated at the frontier of hardware and software.
KEYWORDS: Embedded System; Traceability; Requirement; Specification; Design; Documentation; Virtual Prototype; Software; Hardware; SystemC; IP-XACT
Mobileye Case Study: Using Arteris IP for ADAS In this 4-page paper, created with the participation of Mobileye, you will learn how the world's #1 vision-based automotive ADAS company uses Arteris IP FlexNoC interconnect IP to address demanding high bandwidth and low-latency requirements.
KEYWORDS: Network-on-Chip (NoC); end-to-end QoS; timing closure

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Videos

Title Summary
arteris harmony trace instroduction video

 

Arteris® Harmony Trace™ Introduction Video

Paul Graykowski, senior technical marketing manager at Arteris IP, describes the Arteris Harmony Trace product in this short introductory video.

Why Traceability Matters

 

 Why Traceability Matters
 (Semiconductor Engineering)

Paul Graykowski, senior technical marketing manager at Arteris IP, talks to Semiconductor Engineering about matching requirements to the design, the impact of ECOs and other last-minute changes, and best practices for managing revisions.

sddefault-1 Changes in AI SoCs

Kurt Shuler, vice president of marketing at Arteris IP, talks with Semiconductor Engineering about the tradeoffs in AI SoCs, which range from power and performance to flexibility, depending on whether processing elements are highly specific or more general, and the need for more modeling.

sddefault CXL vs CCIX

Kurt Shuler, vice president of marketing at Arteris IP, talks with Semiconductor Engineering on how these two standards differ, which ones work best where, and what each was designed for.

what-is-sotif-tech-talk-shuler What is SOTIF? - Tech Talk
(Semiconductor Engineering)

Arteris IP’s Kurt Shuler discusses new system-level best-practices for automotive design that will be used for both diagnostics and forensics when something goes wrong with autonomous vehicles.
KEYWORDS: SOTIF; ISO/PAS 21448; ISO 26262; autonomous driving; ADAS

ai-tech-talk-video-shuler AI Training Chips - Tech Talk
(Semiconductor Engineering)

Arteris IP’s Kurt Shuler describes AI training chip architectures, how different processing elements are used to accelerate training algorithms, and how to achieve improved performance.
KEYWORDS: Artificial intelligence (AI); neural networks; machine learning (ML)

kurt-shuler-iso26262-tech-talk
ISO 26262 Drilldown - Tech Talk
(Semiconductor Engineering)

Arteris IP’s Kurt Shuler describes about what's required to gain a solid foothold in the automotive electronics market.
KEYWORDS: ISO 26262; ASIL; autonomous driving; ADAS

2018-07-19-arteris-ip-7nm-design-challenges 7 nm Design Challenges
(Semiconductor Engineering)
Why the next nodes will be so expensive, and how they will play out in chip design
KEYWORDS: Semiconductor process technology
2018-07-19-dac-automotive-ai Arteris IP Interconnect for AI and Automotive Solutions
(Design & Reuse at DAC)

Arteris IP’s Kurt Shuler looks at what can go wrong in automotive design, what are the prerequisites for getting the attention of Tier 1s and OEMs, and what’s involved in automotive design at all levels.
KEYWORDS: ISO 26262 certification; ASIL D; autonomous driving; ADAS

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Articles