|A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow
||This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation.
KEYWORDS: Network-on-Chip (NoC); Routing congestion; physical design
|A Design Flow for Critical Embedded Systems
||In this paper by Airbus, Thales, STMicroelectronics, Arteris IP and other, learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems.
KEYWORDS: DO-178C, DO-254, ARP4754, ECSS Q60-02, Q80, E40, High-Level Synthesis, SystemC/TLM, IP-XACT, Assertion-Based Verification (ABV), Property Specification Language (PSL)
|A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis
||This paper presents a lightweight and cost-effective approach to power estimation suitable for software developers. It relies on trace analysis and high-level modeling of architectures to perform quick and efficient power consumption estimations without losing accuracy.
KEYWORDS: power consumption; embedded software design; power management; trace analysis
|A SystemC Extension for Enabling Tighter Integration of IP-XACT Platforms with Virtual Prototypes
||This paper describes a configurable SystemC extension that simplifies the syntax for expressing register and bitfield accesses and enables automation of virtual platform and hardware-software interface (HSI) development.
KEYWORDS: SystemC, Virtual Hardware Prototyping, IP-XACT, code generation
|AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases
||This 12-page paper published in the peer-reviewed IEEE Design & Test journal explains how Universal Verification Methodology (UVM), initially developed for digital systems, can be extended to analog and mixed signal systems with the help if IP-XACT-based IP packaging and design flow automation.
KEYWORDS: Coverage Driven Verification (CDV), Design Under Test (DUT), Electronic Control Unit (ECU), Electronic System Level (ESL), functional verification, Hardware In the Loop (HIL), system simulation, SystemC, SystemC-AMS, Timed Data Flow (TDF), Transaction Level Modeling (TLM), Universal Verification Methodology (UVM), system verification, Virtual Prototyping (VP)
|Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC
||Peer-reviewed technical journal article from Springer's "Design Automation for Embedded Systems Journal." Summarizes the various features a NoC is required to implement to be integrated in modern SoCs. Describes a top-down approach, based on the progressive refinement of the NoC description from its functional specification (Sect. 4) to its verification (Sect. 8).
KEYWORDS: Network-on-Chip (NoC); Quality-of-Service (QoS); Routing
|Building a Portable Stimulus Flow Based on Magillem IP-XACT Packaging
||This paper written by Nokia and Mentor Siemens describes an efficient integration flow using Portable Stimulus and IP-XACT flow automation.
KEYWORDS: IP-XACT, portable stimulus, verification intent, design under test (DUT)
|CodaCache: Helping to Break the Memory Wall
||This paper describes a novel configurable last level cache IP, CodaCache, that provides an easy-to-integrate solution giving system architects the capability to configure and adapt to their specific needs. Key technologies implemented in this IP are per-master way partitioning, scratchpad RAM allocation, AXI interfaces and functional safety mechanisms.
|Easing Heterogeneous Cache Coherent SoC Design using Arteris’ Ncore Interconnect
||From The Linley Group, publisher of Microprocessor Report. 9-page paper explains new hardware interconnect IP technology that enables cache coherent communication between different types of compute engines in and SoC.
KEYWORDS: Cache coherence; Proxy cache; Network-on-Chip (NoC);
|Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product
||Written by an ISO 26262 working group member who contributed to the new ISO 26262:2018 Part 11, this paper dispels myths about ISO 26262 certification and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.
KEYWORDS: ISO 26262 certification; ASIL; FMEDA
|Generation of UVM Compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS
||This paper presents a methodology and flow to automate the test bench creation for automotive heterogeneous HW/SW systems, using SystemC, SystemC-AMS and IP-XACT.
KEYWORDS: Simulation; Verification; EDA Automation; SystemC; SystemC-AMS; IP-XACT; UVM
|How to Efficiently Achieve ASIL-D Compliance Using NoC Technology
||A closer look at ASIL-D compliance options for on-chip interconnects and NoCs, including redundancy, path diversity and error correction codes (ECC) is required to fully optimize an on-chip network to meet rapidly evolving technology and customer demands.
KEYWORDS: Network-on-chip (NoC); ISO 26262; functional safety; redundancy; ECC
|HW / SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures
||This paper presents a code generation flow to deploy system applications over hardware architectures based on abstract descriptions.
KEYWORDS: HW/SW Interface, IP-XACT, hardware abstraction layer (HAL)
|Optimizing Enterprise-Class SSD Host Controller Design with Arteris FlexNoC Network-On-Chip Interconnect IP
||Enterprise SSD Endurance & Data Protection technical paper that explains how the leading enterprise SSD controller design teams are using network-on-chip (NoC) interconnect technology to optimize their designs for power consumption and performance while increasing reliability and availability.
KEYWORDS: Network-on-chip (NoC); routing congestion; SSD
|Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding
||An oldie but a goodie: Explains power benefits of NoC technology by characterizing a multi-processor system-on-chip (MPSoC) for MPEG4, AVC/H.264 encoding. Explains NoC power model used to analyze power consumption and dissipation.
KEYWORDS: Network-on-chip (NoC); power consumption
|Re-Architecting SoCs for the AI Era
||This paper defines AI, describe its applications, the problems it presents, and how chip designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design.It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.
KEYWORDS: Artificial Intelligence (AI), Machine Learning (ML), Dataflow, ISO 26262, Functional Safety, Semiconductor
|Reinventing Traceability: Adding Domain Intelligence with Arteris Harmony Trace™
||This paper proposes and explains the Arteris Harmony Trace solution which Increases system quality and functional safety assessments by identifying and fixing the traceability gaps between disparate systems.
KEYWORDS: Traceability; IP-XACT; Requirements; EDA Automation; Functional Safety; Quality; ISO 26262; IEC 61508; ISO 9001; IATF 16949
|Routing Congestion: The Growing Cost of Wires
||The congestion of wires in the place and route (P&R) stage of chip design poses an increasingly significant challenge to creating low cost, high performance chip designs. This paper introduces packet based network-on-chip as a means of enabling configuration link widths, shows experimental results, and describes other benefits of packet-based interconnect networks.
KEYWORDS: Network-on-Chip (NoC); Routing congestion; physical design
|Scalability - A Looming Problem in Safety Analysis
||Misbehavior in the electronics can lead to accidents, even fatalities. This paper describes how ISO 26262 standard and in particular the Failure Modes, Effects and Diagnostic Analysis (FMEDA) can be leveraged to address this real concern.
KEYWORDS: FMEDA; ISO 26262; Traceability; IEEE P2851
|Using Machine Learning for Characterization of NoC Components
||This Award Winning Paper was presented at Synopsys SNUG Silicon Valley 2019. You will learn about modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters. PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized.
KEYWORDS: ML, PPA,
|Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP
||Principles and real-world practices of ISO 26262 for semiconductor design teams. Explains how configuration in IP design can be used as an advantage to automatically drive fault injection using Synopsys Z01X tools. We will demonstrate using a real case study of diagnostic coverage, FMEDA creation and ASIL determination for a fully configurable IP.
KEYWORDS: Synopsys Z01X; fault injection; FMEDA; ASIL; ISO 26262
|Using Virtual Prototypes to Improve the Traceability of Critical Embedded Systems Flow
||This paper written with Imperas explains how the combination of innovative traceability techniques with an advanced virtual prototyping execution environment helps to detect and locate critical embedded system bugs situated at the frontier of hardware and software.
KEYWORDS: Embedded System; Traceability; Requirement; Specification; Design; Documentation; Virtual Prototype; Software; Hardware; SystemC; IP-XACT
|Mobileye Case Study: Using Arteris IP for ADAS
||In this 4-page paper, created with the participation of Mobileye, you will learn how the world's #1 vision-based automotive ADAS company uses Arteris IP FlexNoC interconnect IP to address demanding high bandwidth and low-latency requirements.
KEYWORDS: Network-on-Chip (NoC); end-to-end QoS; timing closure