Datasheets

Title Type Summary
Arteris IP SoC HSI Development Datasheet-lg-shadow

 

SoC & Hardware / Software Interface (HSI) Development Datasheet Datasheet,
2 pages
  • Productivity: Get all product teams on the same development platform. Replace ad-hoc scripts, local know-how, empower true innovation
  • Manage risk: Reliable scalability for larger designs, derivatives demanding a shorter schedule. Follow industry leaders in mobile, automotive, others
  • Collaboration: Easily collaborate with other design teams and partners
Arteris IP Harmony Trace Datasheet-2586x3336-border

 

Arteris® Harmony Trace™ Datasheet Datasheet,
2 pages
  • Increases system quality and functional safety assessments by identifying and fixing the traceability gaps between disparate systems
  • Unique because it gives engineers the freedom to use the “best tool for the job” and automates linking requirements and artifacts
  • Implemented as an enterprise-level server-based application with a web-based user interface (UI)
Arteris IP Product Information Management Datasheet-300-shadow

 

Product Information
Management Datasheet
Datasheet,
2 pages
  • Provide partners datasheets in real-time: Generate key parametric documentation at any time from in-process designs
  • Quality: Ensure all documentation & specifications are fully in sync with latest updates to the design
  • Compatibility: Standard formats are easily integrated with Tech Pubs systems
AIP FlexNoC datasheet 2018-08-16-003-2552x3302-border FlexNoC® Datasheet Datasheet,
2 pages
  • Non-coherent network-on-chip (NoC) interconnect IP
  • Protocol interoperability: AMBA AXI, AHB, APB, OCP, PIF; custom / proprietary
  • Reduce wire routing congestion, die area & power consumption
  • Meets ISO 26262 ASIL D requirements
Arteris IP FlexNoC Resilience Package Datasheet-lg-shadow

 

FlexNoC® Resilience Package Datasheet Datasheet,
2 pages
  • Adds safety mechanisms to FlexNoC IP
  • ECC, hardware unit duplication
  • Adds safety controller
  • Adds FMEDA output
AIP FlexNoC AI datasheet 2018-10-31-001-2552x3302-border FlexNoC® AI Package Datasheet Datasheet,
2 pages
  • Mesh, ring and torus topology generation and editing
  • Efficient multicast and broadcast
  • VC-Link™ virtual channels; Source synchronous communications
  • HBM2 support
  • Optional Resilience Package to meet ISO 26262 ASIL D functional safety requirements
  • Optional PIANO Timing Closure Package to automate timing closure with floorplan information
AIP Ncore datasheet 2018-08-16-005-2552x3302-border Ncore® Datasheet Datasheet,
2 pages
  • Cache coherent network-on-chip (NoC) interconnect IP
  • Arm® AMBA® CHI and ACE interoperability; CCIX protocol support for multi-chip systems
  • ISO 26262-compliant functional safety mechanisms
AIP CodaCache datasheet 2018-08-16-001-2552x3302-border CodaCache™ Datasheet Datasheet,
2 pages
  • Standalone, highly configurable last level cache
  • Arm® AMBA® AXI compliant
  • Configurable way partitioning, sizing, & scratchpad configurations

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Presentations

Title Type Summary
2020-04-09-Linley-Spring-2020-Arteris IP-Implementing Low-Power AI SoCs Implementing Low-Power AI SoCs Using NoC Interconnect Technology

Conference Presentation, 15 slides

Presented at The Linley Spring Processor Conference 2020, describes lessons learned using network-on-chip (NoC) technology to implement AI processing SoCs that meet explosive bandwidth and tight latency requirements while meeting stringent power consumption needs.
KEYWORDS: AI/ML, neural network, low power

snug-machine-learning-ml-noc-characterization-2488x1440-border-shadow

 

Using Machine Learning for Characterization of NoC Components

Conference Presentation, 33 slides

This Award Winning Paper was presented at Synopsys SNUG Silicon Valley 2019. You will learn about modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters.  PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized.
KEYWORDS: ML, PPA

2019-12-03-IQPC Dec 2019-Automotive AI ML Lessons Learned - Arteris IP-962x542-border Lessons Learned Integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip

Conference Presentation, 18 slides

Presented at the ISO 26262 for Semiconductors (Munich) Conference, this presentation describes the differences between "regular" and AI-enabled automotive chips in the following dimensions: PPA, Safety and Schedule.
KEYWORDS: ISO 26262, AI/ML, functional safety, fault injection, neural network

2019-10-08-Arm TechCon 2019 Hopkins_Benndorf_Shuler_Final V3_10.7.19_Page_01

 

Arm TechCon: Implementing ISO 26262 Compliant AI System-on-Chip with Arm and Arteris IP

Conference Presentation, 46 slides

Arm, Arteris IP, and Dream Chip Technologies joint presentation from Arm TechCon 2019 explains IP integration requirements for AI subsystems in ISO 26262-compliant chips. With an emphasis on techniques and safety mechanisms to enhance the diagnostic coverage of SoCs integrating an NPU and Safety Island. Topic areas include system design to comply with ISO 26262, system-level diagnostics, Network-on-Chip (NoC) safety mechanisms, subsystem isolation, and end-to-end error protection.
KEYWORDS: ISO 26262, functional safety, automotive, neural network
2018-11-30-Arm Arteris IP joint presentation ICCAD China Zhuhai 2018 opt-001 Arm & Arteris IP AI and ISO 26262 Presentation

Conference Presentation, 22 slides

Arm & Arteris IP joint presentation from ICCAD China 2018 describes how new artificial (AI) and machine learning (ML) acceleration IP from Arm, like the Arm(R) NPU and Mali (TM) C71, can be implemented in ISO 26262-compliant automotive systems with the help of functional safety mechanisms in the Arteris IP FlexNoC and Ncore interconnects.
KEYWORDS: IOS 26262, functional safety, automotive, neural network
landing page what to expect iso 26262 ISO 26262: What to Expect from your Chip or IP Provider

Conference presentation,15 slides

This Automotive IQ "Guidance of ISO 26262 to Semiconductors" presentation provides "lessons learned" regarding ISO 26262 deliverables that Tier-1s and semiconductor vendors should expect from their suppliers along with practical advice given regarding the DIA and Safety Manual contents as well as FMEDA expectations for configurable IP.
KEYWORDS: ISO 26262, FMEDA, FMEA
2018-06-11-FMEA before FMEDA ISO 26262: FMEA before FMEDA

Conference presentation, 36 slides

This Automotive IQ "Guidance of ISO 26262 to Semiconductors" presentation includes, develop, plan analyze, merge, and validate failure mode effects (FMEA) creation flow. IP architecture and best practices, examples of element decomposition, and merging element analysis and much more.
KEYWORDS: ISO 26262, FMEA, FMEDA, safety mechanisms, fault injection 
Screenshot-Architecting-Future-of-Deep-Learning Architecting the Future of Deep Learning Presentation

Keynote Presentation,
26 slides

Learn about the history of artificial intelligence (AI), machine learning, (ML), and deep learning. Keynote presentation at the 2018 eSilicon "ASICs Unlock Deep Learning Innovation" seminar. 
KEYWORDS: Artificial intelligence (AI); machine learning (ML); neural networks (NN);  deep learning
2018-03-16-Arteris-IP-ResilTech-AutomotiveIQ-ISO-26262-Dusseldorf-IQPC-opt-FINAL 67-067-4002x2252-border ISO 26262 System-on-Chip (SoC) Safety Analysis for ADAS and AV Conference Workshop Presentation,
93 slides
Training materials for the 3-hour workshop at the Automotive IQ 8th Annual ISO 26262 for Conference in Dusseldorf, Germany. Explains how explains how SoC integrators validate FMEDA metrics using fault simulators and EDA simulations, and how system design teams can take advantage of these results to optimize the system-level safety concept.
KEYWORDS: ISO 26262; FMEDA; fault injection
ArmTechCon-ISO26262-fundamental-ArterisIP-ResilTech_Page_35 Fundamentals of ISO 26262 Part 11 for Semiconductors Conference Presentation,
39 slides
Arm TechCon presentation that describes what is new in ISO 26262 2nd Edition Part 11, "Guidelines on application of ISO 26262 to semiconductors."
KEYWORDS: ISO 26262; diagnostic coverage; FMEDA;  and ASIL tailoring
landing-page-iso-26262-challenges-fault-simulation Challenges Adopting Fault Injection to Support Safety Analysis in Complex SoCs Conference Presentation, 39 slides Learn about fault simulator and EDA tools requirements; Using FMEA to create fault injection campaign; Guidelines/lesson learned for simulating different fault types; Analysis and documentation.
KEYWORDS: ISO 26262, SoCs, FMEA, fault, safety
ArterisIP - implementing machine learning and neural network chip architectures-602x340-border Implementing Machine Learning & Neural Network Chip Architectures Presentation,
17 slides
Presentation describes types processing elements for neural net acceleration, current state-of-the-art AI SoC architectures, and influence of interconnect and memory architectures on AI data flow.
KEYWORDS: Artificial intelligence (AI); machine learning (ML); neural networks (NN);  hardware acceleration
axi_nic-400_routing_congestion-resized-167 Routing Congestion: The Growing Cost of Wires Conference Presentation,
17 slides

Arm TechCon presentation that describes the benefits of benefits of packet-based on-chip interconnect networks.
KEYWORDS: network-on-chip (NoC); routing congestion

50_snug_2018_presentation_final Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP Conference Presentation,
37 slides
Principles and real-world practices of ISO 26262 for semiconductor design teams. Explains how configuration in IP design can be used as an advantage to automatically drive fault injection using Synopsys Z01X tools. We will demonstrate using a real case study of diagnostic coverage, FMEDA creation and ASIL determination for a fully configurable IP.
KEYWORDS: Synopsys Z01X; fault injection; FMEDA; ASIL

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Technical Papers

Title Type Summary
snug-2019-NoC machine learning characterization-paper-border-shadow Using Machine Learning for Characterization of NoC Components

Conference Paper, 19 pages

This Award Winning Paper was presented at Synopsys SNUG Silicon Valley 2019. You will learn about modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters.  PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized.
KEYWORDS: ML, PPA, 

ATP 876653-24365 Harmony Trace Reinventing Traceability 2021-11-14-01-border-shadow

 

Reinventing Traceability: Adding domain intelligence with Arteris® Harmony Trace™

Paper, 11 pages

This paper proposes and explains the Arteris Harmony Trace solution which Increases system quality and functional safety assessments by identifying and fixing the traceability gaps between disparate systems.
KEYWORDS: Traceability; IP-XACT; Requirements; EDA Automation; Functional Safety; 
Quality; ISO 26262; IEC 61508; ISO 9001; IATF 16949

Arteris IP-CEA-LETI-MINATEC-Power Consumption Estimation Trace Analysis IP-XACT

 

A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis

Paper, 8 pages

This paper presents a lightweight and cost-effective approach to power estimation suitable for software developers. It relies on trace analysis and high-level modeling of architectures to perform quick and efficient power consumption estimations without losing accuracy. 
KEYWORDS: power consumption; embedded software design; power management; trace analysis

Arteris IP-Continental-NXP-LIP6-UVM-Test-Benches-IP-XACT-Automotive-Systems

 

Generation of UVM compliant Test Benches for Automotive Systems using IP-XACT with UVM-SystemC and SystemC AMS

Paper, 8 pages

This paper presents a methodology and flow to automate the test bench creation for automotive heterogeneous HW/SW systems, using SystemC, SystemC-AMS and IP-XACT.
KEYWORDS: Simulation; Verification; EDA Automation; SystemC; SystemC-AMS; IP-XACT; UVM

Arteris IP-DVCon- A SystemC Extension for Enabling Tighter Integration of IP-XACT Platforms with Virtual Prototypes

 

A SystemC Extension for Enabling Tighter Integration of IP-XACT Platforms with Virtual Prototypes

Paper, 6 pages

This paper describes a configurable SystemC extension that simplifies the syntax for expressing register and bitfield accesses and enables automation of virtual platform and hardware-software interface (HSI) development.
KEYWORDS: SystemC, Virtual Hardware Prototyping, IP-XACT, code generation

Arteris IP-Nokia-Mentor-Building a Portable Stimulus flow based on Magillem IP-XACT Packaging

 

Building a Portable Stimulus flow based on Magillem IP-XACT Packaging

 Paper, 9 pages

This paper written by Nokia and Mentor Siemens describes an efficient integration flow using Portable Stimulus and IP-XACT flow automation.
KEYWORDS: IP-XACT, portable stimulus, verification intent, design under test (DUT)

ATP 5873961-94086 Arteris IP CodaCache - Tech Paper_Page_1-2552x3302-border-2584x3334-shadow CodaCache: Helping to Break the Memory Wall

Paper, 7 pages

This paper describes a novel configurable last level cache IP, CodaCache, that provides an easy-to-integrate solution giving system architects the capability to configure and adapt to their specific needs. Key technologies implemented in this IP are per-master way partitioning, scratchpad RAM allocation, AXI interfaces and functional safety mechanisms.

arteris_daes_application_driven_noc_ds167
Application Driven Network-on Chip Architecture Exploration & Refinement for a Complex SoC 

Peer-Reviewed Paper,
26 pages

Peer-reviewed technical journal article from Springer's "Design Automation for Embedded Systems Journal."  Summarizes the various features a NoC is required to implement to be integrated in modern SoCs. Describes a top-down approach, based on the progressive refinement of the NoC description from its functional specification (Sect. 4) to its verification (Sect. 8).
KEYWORDS: Network-on-Chip (NoC); Quality-of-Service (QoS); Routing

linley-group-arteris-ncore-white-paper-cover-pic-189px Easing Heterogeneous Cache Coherent SoC Design using Arteris’ Ncore Interconnect Microprocessor Report / Linley Group Paper,
9 pages
From The Linley Group, publisher of Microprocessor Report. 9-page paper explains new hardware interconnect IP technology that enables cache coherent communication between different types of compute engines in and SoC.
KEYWORDS: Cache coherence; Proxy cache; Network-on-Chip (NoC);
ATP 8732453-93753 Re-Architecting SoCs for AI Era - Tech Paper - FINAL - image Re-Architecting SoCs for the AI Era Paper,
10 pages

This paper defines AI, describe its applications, the problems it presents, and how chip designers can address those problems through new and holistic approaches to SoC and network on chip (NoC) design.It also describes challenges implementing AI functionality in automotive SoCs with ISO 26262 functional safety requirements.
KEYWORDS: Artificial Intelligence (AI), Machine Learning (ML), Dataflow, ISO 26262, Functional Safety, Semiconductor 

Routing Congestion-The Growing Cost of Wires-001-2552x3302-border Routing Congestion: The Growing Cost of Wires Paper,
13 pages

The congestion of wires in the place and route (P&R) stage of chip design poses an increasingly significant challenge to creating low cost, high performance chip designs. This paper introduces packet based network-on-chip as a means of enabling configuration link widths, shows experimental results, and describes other benefits of packet-based interconnect networks.
KEYWORDS: Network-on-Chip (NoC); Routing congestion; physical design

Arteris IP-CEA-LETI-MINATEC-TIMA-TC06-HWSW-Interface-Generation-Flow-Based-on Abstract-Models

 

HW / SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures Paper,
11 pages

This paper presents a code generation flow to deploy system applications over hardware architectures based on abstract descriptions.
KEYWORDS: HW/SW Interface, IP-XACT, hardware abstraction layer (HAL)

Arteris IP-IEEE-NXP-Infineon-Continental-LIP6-TC11-AMS UVM in SystemC and SystemC-AMS for Automotive

 

AMS System-Level Verification and Validation using UVM in SystemC and SystemC AMS: Automotive Use Cases Paper,
12 pages

This 12-page paper published in the peer-reviewed IEEE Design & Test journal explains how Universal Verification Methodology (UVM), initially developed for digital systems, can be extended to analog and mixed signal systems with the help if IP-XACT-based IP packaging and design flow automation.
KEYWORDS: Coverage Driven Verification (CDV), Design Under Test (DUT), Electronic Control Unit (ECU), Electronic System Level (ESL), functional verification, Hardware In the Loop (HIL), system simulation, SystemC, SystemC-AMS, Timed Data Flow (TDF), Transaction Level Modeling (TLM), Universal Verification Methodology (UVM), system verification, Virtual Prototyping (VP)

Arteris IP-Imperas-embeddedworld-Using Virtual Prototypes to Improve the Traceability

 

Using Virtual Prototypes to Improve the Traceability of Critical Embedded Systems Flow Paper,
4 pages

This paper written with Imperas explains how the combination of innovative traceability techniques with an advanced virtual prototyping execution environment helps to detect and locate critical embedded system bugs situated at the frontier of hardware and software.
KEYWORDS: Embedded System; Traceability; Requirement; Specification; Design; Documentation; Virtual Prototype; Software; Hardware; SystemC; IP-XACT

Arteris IP-NXP-A-Configurable-Test-Infrastructure IP-XACT

 

A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow Paper,
7 pages

This paper written with NXP describes an efficient integration flow for mixed-language and mixed-abstraction level IPs through IP-XACT flow automation.
KEYWORDS: Network-on-Chip (NoC); Routing congestion; physical design

Arteris IP-STMicro-Thales-Airbus-MDS-TC07-A-Design-Flow-for-Critical-Embedded-Systems

 

A Design Flow for Critical Embedded Systems Paper,
5 pages

In this paper by Airbus, Thales, STMicroelectronics, Arteris IP and other, learn how IP encapsulation/packaging and interoperability using IP-XACT enabled automation in a complex verification & validation flow for aeronautical systems.
KEYWORDS: DO-178C, DO-254, ARP4754, ECSS Q60-02, Q80, E40, High-Level Synthesis, SystemC/TLM, IP-XACT, Assertion-Based Verification (ABV), Property Specification Language (PSL)

mobileye-adas-case-study-screenshot

 

Mobileye Case Study: Using Arteris IP for ADAS Paper,
4 pages

In this 4-page paper, created with the participation of Mobileye, you will learn how the world's #1 vision-based automotive ADAS company uses Arteris IP FlexNoC interconnect IP to address demanding high bandwidth and low-latency requirements.
KEYWORDS: Network-on-Chip (NoC); end-to-end QoS; timing closure

ATP 876323-21423 ISO 26262 Certification Fundamentals - Tech Paper-001-2552x3302-border Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product Paper,
18 slides
Written by an ISO 26262 working group member who contributed to the new ISO 26262:2018 Part 11, this paper dispels myths about ISO 26262 certification and seeks to enhance the reader’s knowledge regarding all aspects of the ISO 26262 standard. This paper also discusses the standard’s applicability not only to electronic products, but also to the people and processes employed to create them.
KEYWORDS: ISO 26262 certification; ASIL; FMEDA
enterprise-ssd-controller-tech-paper-arteris Optimizing Enterprise-Class SSD Host Controller Design with Arteris FlexNoC Network-On-Chip Interconnect IP Paper,
11 pages

Enterprise SSD Endurance & Data Protection technical paper that explains how the leading enterprise SSD controller design teams are using network-on-chip (NoC) interconnect technology to optimize their designs for power consumption and performance while increasing reliability and availability.
KEYWORDS: Network-on-chip (NoC); routing congestion; SSD

How to efficiently achieve ASILD compliance using NoC Technology_July 2018-001-2482x3250-border IEEE: How to Efficiently Achieve ASIL-D Compliance Using NoC Technology IEEE-published paper, 
3 pages

A closer look at ASIL-D compliance options for on-chip interconnects and NoCs, including redundancy, path diversity and error correction codes (ECC) is required to fully optimize an on-chip network to meet rapidly evolving technology and customer demands.
KEYWORDS: Network-on-chip (NoC); ISO 26262; functional safety; redundancy; ECC

 SNUG-paper-border-1 Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a fully Configurable IP  Conference paper, 
17 pages
Principles and real-world practices of ISO 26262 for semiconductor design teams. Explains how configuration in IP design can be used as an advantage to automatically drive fault injection using Synopsys Z01X tools. We will demonstrate using a real case study of diagnostic coverage, FMEDA creation and ASIL determination for a fully configurable IP.
KEYWORDS: Synopsys Z01X; fault injection; FMEDA; ASIL; ISO 26262
ieee_noc_power_dissipation_sm-resized-167 Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding IEEE peer-reviewed paper,
4 pages
An oldie but a goodie: Explains power benefits of NoC technology by characterizing a multi-processor system-on-chip (MPSoC) for MPEG4, AVC/H.264 encoding. Explains NoC power model used to analyze power consumption and dissipation.
KEYWORDS: Network-on-chip (NoC); power consumption

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Videos

Title Type Summary
arteris harmony trace instroduction video

 

Arteris® Harmony Trace™ Introduction Video

Video, 1 minute

Paul Graykowski, senior technical marketing manager at Arteris IP, describes the Arteris Harmony Trace product in this short introductory video.

sddefault-1 Changes in AI SoCs

Video, 15 minutes

Kurt Shuler, vice president of marketing at Arteris IP, talks with Semiconductor Engineering about the tradeoffs in AI SoCs, which range from power and performance to flexibility, depending on whether processing elements are highly specific or more general, and the need for more modeling.

sddefault CXL vs CCIX

Video, 15 minutes

Kurt Shuler, vice president of marketing at Arteris IP, talks with Semiconductor Engineering on how these two standards differ, which ones work best where, and what each was designed for.

what-is-sotif-tech-talk-shuler What is SOTIF? - Tech Talk
(Semiconductor Engineering)

Video,
11 minutes

Arteris IP’s Kurt Shuler discusses new system-level best-practices for automotive design that will be used for both diagnostics and forensics when something goes wrong with autonomous vehicles.
KEYWORDS: SOTIF; ISO/PAS 21448; ISO 26262; autonomous driving; ADAS

ai-tech-talk-video-shuler AI Training Chips - Tech Talk
(Semiconductor Engineering)

Video,
11 minutes

Arteris IP’s Kurt Shuler describes AI training chip architectures, how different processing elements are used to accelerate training algorithms, and how to achieve improved performance.
KEYWORDS: Artificial intelligence (AI); neural networks; machine learning (ML)

kurt-shuler-iso26262-tech-talk
ISO 26262 Drilldown - Tech Talk
(Semiconductor Engineering)

Video,
20 minutes

Arteris IP’s Kurt Shuler describes about what's required to gain a solid foothold in the automotive electronics market.
KEYWORDS: ISO 26262; ASIL; autonomous driving; ADAS

2018-07-19-arteris-ip-7nm-design-challenges 7 nm Design Challenges
(Semiconductor Engineering)
Video,
20 minutes
Why the next nodes will be so expensive, and how they will play out in chip design
KEYWORDS: Semiconductor process technology
2018-07-19-dac-automotive-ai Arteris IP Interconnect for AI and Automotive Solutions
(Design & Reuse at DAC)
Video,
5 minutes

Arteris IP’s Kurt Shuler looks at what can go wrong in automotive design, what are the prerequisites for getting the attention of Tier 1s and OEMs, and what’s involved in automotive design at all levels.
KEYWORDS: ISO 26262 certification; ASIL D; autonomous driving; ADAS

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Articles