|Architecting the Future of Deep Learning Presentation
||Learn about the history of artificial intelligence (AI), machine learning, (ML), and deep learning. Keynote presentation at the 2018 eSilicon "ASICs Unlock Deep Learning Innovation" seminar.
KEYWORDS: Artificial intelligence (AI); machine learning (ML); neural networks (NN); deep learning
|Arm TechCon: Implementing ISO 26262 Compliant AI System-on-Chip with Arm and Arteris
||Arm, Arteris, and Dream Chip Technologies joint presentation from Arm TechCon 2019 explains IP integration requirements for AI subsystems in ISO 26262-compliant chips. With an emphasis on techniques and safety mechanisms to enhance the diagnostic coverage of SoCs integrating an NPU and Safety Island. Topic areas include system design to comply with ISO 26262, system-level diagnostics, Network-on-Chip (NoC) safety mechanisms, subsystem isolation, and end-to-end error protection.
KEYWORDS: ISO 26262, functional safety, automotive, neural network
|Arm & Arteris AI and ISO 26262 Presentation
||Arm & Arteris joint presentation from ICCAD China 2018 describes how new artificial (AI) and machine learning (ML) acceleration IP from Arm, like the Arm(R) NPU and Mali (TM) C71, can be implemented in ISO 26262-compliant automotive systems with the help of functional safety mechanisms in the Arteris FlexNoC and Ncore interconnects.
KEYWORDS: IOS 26262, functional safety, automotive, neural network
|Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)
||Presented at IQPC Application of ISO 26262 2022 Conference, describes an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics at a level that scales with the size and complexity of an SoC and enables reuse for the creation of SoC platform derivative chips, which is common in our industry.
KEYWORDS: FMEDA, traceability, functional safety, ISO 26262
|Building Better IP with RTL Architect NoC IP Physical Exploration
||Voted one of the “Top Ten Best Presentations” at SNUG Silicon Valley 2023, this presentation discusses the importance of NoCs and their impact on timing analysis and power consumption. It introduces a flow and methodology that utilizes RTL-based estimation of timing and power consumption using RTL Architect in conjunction with Arteris’ FlexNoC 5 and Ncore NoC development frameworks. FlexNoC 5 facilitates up to 5X faster physical convergence of the back-end physical design time and effort.
|Challenges Adopting Fault Injection to Support Safety Analysis in Complex SoCs
||Learn about fault simulator and EDA tools requirements; Using FMEA to create fault injection campaign; Guidelines/lesson learned for simulating different fault types; Analysis and documentation.
KEYWORDS: ISO 26262, SoCs, FMEA, fault, safety
|FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)
||Failure modes, effects, and diagnostic analysis (FMEDA) for sophisticated chips with hundreds of IP blocks are fraught with complexity and opportunities for systematic errors. This presentation will describe an approach that uses a hierarchal and modular library of safety components to describe failure modes, safety mechanism diagnostic coverage, and other functional safety metrics.
KEYWORDS: FMEDA, traceability, functional safety, ISO 26262
|Fundamentals of ISO 26262 Part 11 for Semiconductors
||Arm TechCon presentation that describes what is new in ISO 26262 2nd Edition Part 11, "Guidelines on application of ISO 26262 to semiconductors."
KEYWORDS: ISO 26262; diagnostic coverage; FMEDA; and ASIL tailoring
|Implementing Low-Power AI SoCs Using NoC Interconnect Technology
||Presented at The Linley Spring Processor Conference 2020, describes lessons learned using network-on-chip (NoC) technology to implement AI processing SoCs that meet explosive bandwidth and tight latency requirements while meeting stringent power consumption needs.
KEYWORDS: AI/ML, neural network, low power
|Implementing Machine Learning & Neural Network Chip Architectures
||Presentation describes types processing elements for neural net acceleration, current state-of-the-art AI SoC architectures, and influence of interconnect and memory architectures on AI data flow.
KEYWORDS: Artificial intelligence (AI); machine learning (ML); neural networks (NN); hardware acceleration
|Lessons Learned Integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip
||Presented at the ISO 26262 for Semiconductors (Munich) Conference, this presentation describes the differences between "regular" and AI-enabled automotive chips in the following dimensions: PPA, Safety and Schedule.
KEYWORDS: ISO 26262, AI/ML, functional safety, fault injection, neural network
|Is the Missing Safety Ingredient in Automotive AI Traceability?
||Presented at The Linley Spring Processor Conference 2022, describes the importance of traceability as it applies to managing SoC requirements and customer deliverables whilst also shortening the path to functional safety certification including ISO 26262.
KEYWORDS: traceability, AI/ML, functional safety, ISO 26262, ADAS.
|ISO 26262: FMEA before FMEDA
||This Automotive IQ "Guidance of ISO 26262 to Semiconductors" presentation includes, develop, plan analyze, merge, and validate failure mode effects (FMEA) creation flow. IP architecture and best practices, examples of element decomposition, and merging element analysis and much more.
KEYWORDS: ISO 26262, FMEA, FMEDA, safety mechanisms, fault injection
|ISO 26262: System-on-Chip (SoC) Safety Analysis for ADAS and AV
||Training materials for the 3-hour workshop at the Automotive IQ 8th Annual ISO 26262 for Conference in Dusseldorf, Germany. Explains how explains how SoC integrators validate FMEDA metrics using fault simulators and EDA simulations, and how system design teams can take advantage of these results to optimize the system-level safety concept.
KEYWORDS: ISO 26262; FMEDA; fault injection
|ISO 26262: What to Expect from your Chip or IP Provider
||This Automotive IQ "Guidance of ISO 26262 to Semiconductors" presentation provides "lessons learned" regarding ISO 26262 deliverables that Tier-1s and semiconductor vendors should expect from their suppliers along with practical advice given regarding the DIA and Safety Manual contents as well as FMEDA expectations for configurable IP.
KEYWORDS: ISO 26262, FMEDA, FMEA
|Routing Congestion: The Growing Cost of Wires
||Arm TechCon presentation that describes the benefits of benefits of packet-based on-chip interconnect networks.
KEYWORDS: network-on-chip (NoC); routing congestion
|Safety Considerations for Network-on-Chip (NoC) Development
||This presentation illustrates functional safety challenges in system design and adherence to the ISO 26262 standard for automotive electronics. It highlights Network-on-Chip (NoC) safety mechanisms, including timeouts, IP Block isolation, and end-to-end interface protection.
|Using Synopsys Z01X to Accelerate the Fault Injection Campaign of a Fully Configurable IP
||Principles and real-world practices of ISO 26262 for semiconductor design teams. Explains how configuration in IP design can be used as an advantage to automatically drive fault injection using Synopsys Z01X tools. We will demonstrate using a real case study of diagnostic coverage, FMEDA creation and ASIL determination for a fully configurable IP.
KEYWORDS: Synopsys Z01X; fault injection; FMEDA; ASIL