Use of NoC IP Facilitates Tailoring SoC Platform Design into Bespoke SoC Devices

The Dream Chip team sought to develop an ADAS SoC as a platform reference design that could be easily customized to meet the requirements of multiple customers while also addressing multiple technology nodes. The challenge was to avoid the limitations of off-the-shelf SoCs that may not fulfill specific application needs. Creating a completely new SoC from scratch is expensive, time-consuming and risks missing market opportunities.

Dream Chip needed a solution that allowed them to provide a foundation to create an SoC platform that facilitated rapid modifications and derivative designs. Furthermore, the SoC has to include the Dream Chip automotive ISP.

The Dream Chip team chose to adopt a network-on-chip (NoC) approach, using an on-chip packet-switching network to connect IP blocks within the SoC. The NoC employed special interface functions called sockets. When an IP transmits information, its associated socket translates that IP’s interface protocol into a common packetized and serialized form that will be transported throughout the NoC. Multiple packets can be in flight at the same time. When a packet arrives at its destination, the socket associated with the receiving IP will translate it back into the protocol employed by that IP.

By implementing this approach, the team was able to overcome challenges related to a variety of data widths, various clock frequencies and differing protocols such as OCP, APB, AHB, AXI, STBus and DTL. The NoC facilitated efficient data transmission, reduced routing congestion and improved performance while consuming less power. For platform reference designs, NoCs offered flexibility in adding or removing IPs.

Dream Chip selected Arteris FlexNoC as their NoC solution. “Developing an in-house NoC would have required significant time and resources,” said Darius Grantz, Senior Director Program & Product Management at Dream Chip Technologies. “Additionally, other third-party NoCs did not offer the necessary safety compliance.”

Arteris FlexNoC’s functional safety (FuSa) option provided the required reliability for automotive ISO 26262 or IEC 61508 compliance. FlexNoC’s configurability and ease of use saved design time, allowing Dream Chip to effectively meet customers’ unique requirements.

Dream Chip’s collaboration with Arteris has yielded significant results. The platform reference designs based on FlexNoC have enabled Dream Chip to deliver tailored SoC solutions to multiple customers in a timely manner. The successful tape out of the initial automotive reference design platform served as the basis for subsequent customer derivative designs. Implemented in 22nm FDSOI technology, the die measured 62.77mm2 and contained 1.15 billion transistors. The SoC included a quad-core 64-bit Arm Cortex-A53 processor, a dual-core lock-step 32-bit Arm Cortex-R5 processor, 4 Vision P6 DSP for image processing and a Dream Chip ISP.

Based on this success, Dream Chip developed a new reference design platform as part of the government-funded ZuSE-KI-Mobil (ZuKIMo) research project implementing five FlexNoC interconnects with a die size of 93.03mm2 and more than 1.8 billion transistors.

The updated platform replaced the Arm Cortex-A53 processor with a more powerful Arm Cortex-A65AE including split-lock support and replaced the pure Vision DSP with Vision DSP with AI capabilities (accelerator) and additional custom built AI engine, offering a total 10 TOPS INT8. An updated safety island features a dual Arm Cortex-R52 split-lock core. The platform expands camera support from 4 up to 16, with the latest ASIL B/D Dream Chip ISP supporting 26-bit, HDR, and enhanced local tone mapping providing 3D object detection, image de-warping, and a bird’s eye view of the vehicle’s surrounding. For the latest design, the central NoCs and the NoCs for the DRAMs and Image Signal Processing (ISP) were enhanced and optimized for their use case requirements to support different levels of QoS, ASIL B, and ASIL D, or high speed or combination of them. The reference design platform was successfully taped out and is currently being evaluated by the project partners for automotive ADAS and machine vision solutions.

With the recent release of the new reference design platform, Dream Chip has expanded its capabilities, offering enhanced processing power, increased camera support, and advanced features for ADAS and machine vision applications.

Dream Chip credits the smooth evolution from the original platform reference design to the current version and the ongoing development of the next-generation platform to the effectiveness of FlexNoC from Arteris. The NoC’s flexibility and configurability have greatly facilitated the modification and customization, enabling bespoke SoC designs to meet each customer’s unique requirements. Dream Chip emphasizes that Arteris IP technology is far superior to other available NoC solutions, providing the necessary safety compliance, ease of use and the option to configure each sub NoC to the specific needs and requirements.

Looking ahead, Dream Chip is already working on the next advanced platform that incorporates lidar and radar sensor processing alongside cameras. The ongoing partnership with Arteris ensures that Dream Chip can continue to leverage the benefits of FlexNoC, enabling them to stay at the forefront of innovative SoC design and deliver cutting-edge solutions to their customers.

In conclusion, Arteris has played a crucial role in Dream Chip’s journey of developing tailored SoC platforms for automotive ADAS applications for significant customers in the automotive market. The use of NoC technology, specifically FlexNoC, provides flexibility, FuSa compliance and ease of use to accelerate the development process. Dream Chip Technologies’ successful platform reference designs, powered by FlexNoC from Arteris, have positioned them as a leading provider of bespoke SoC solutions in the automotive industry. Dream Chip and its partners will be demonstrating the SoC at various tradeshows and conferences.