RISC-V and Arteris: Shaping the future of chip design
Unleashing innovation, simplifying connectivity, and driving a new era of specialized semiconductors with plug-and-play network-on-chip connectivity.
Overview
Freedom to innovate smarter devices
As the world demands smarter, more specialized devices, RISC-V offers the freedom to innovate and enables specialization, particularly in AI and machine learning, for automotive, enterprise computing, consumer, communications, and industrial applications. With RISC-V, developers can customize and innovate solutions for specific needs, selecting best-in-class tools and partners to bring their visions to life.
Arteris is a leading partner in the chip design ecosystem, with over 20 years of experience providing plug-and-play solutions to connect hundreds of reused and custom-designed blocks through its network-on-chip (NoC) technology.
While designers focus on their unique differentiation in innovating RISC-V cores, Arteris helps ensure that devices not only work but work efficiently by:
- Enabling the seamless integration of RISC-V cores with other IP blocks
- Unifying NoC protocols
- Handling the complexities of inter- and intra-chip connectivity
- De-risking complex projects
- Speeding up the design-to-market process
Additionally, Arteris collaborates closely with IP partners to ensure seamless interaction between chip components. Our combined expertise co-optimizes design aspects, ensuring that computing and transportation systems work harmoniously. The RISC-V movement, driven by partners like Arteris, is poised to transform the semiconductor landscape in a world that craves more innovative and faster devices.
Advantages
Experience where it matters. Everywhere.
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Seamless integration
Arteris network-on-chip technology helps ensure effortless RISC-V core integration with other IP blocks, making devices functional and efficient.
Expertise in connectivity
With over 20 years of experience, Arteris simplifies the complexities of inter-chip and intra-chip connectivity, enabling designers to focus on core innovation, while accelerating the design-to-market process.
Scalability
Arteris enables designers to create highly scalable ring, mesh, and torus topologies and edit generated topologies, in contrast to black box compiler approaches. This optimizes each individual network router.
The Damo Wujian Alliance, spearheaded by Damo Academy (an affiliate of Alibaba Group), is an ecosystem alliance driving the adoption and development of the RISC-V instruction-set architecture. The coalition focuses on high-performance system-on-chip (SoC) designs, particularly in edge AI computing. As part of the alliance, Arteris plays a pivotal role by enabling the integration of Damo Academy’s / T-Head’s Xuantie RISC-V processor IP cores with its Ncore cache coherent NoC system IP, resulting in efficient data transport architectures within cores and between chips, enabling cutting-edge applications in AI, machine learning, and more.
Design for next-gen demands with Ncore Cache Coherent NoC IP
Ncore is the only scalable, highly configurable, ISO 26262 certified cache coherent NoC for modern SoC designs.
- Any processor
- Multiple protocols
- Flexible configuration
Maximize engineering productivity and accelerate time-to-market with Ncore. Our white paper shows how you could save 50+ person years over a DIY project.
Products
Products for RISC-V designs
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Customers
Trusted by innovative companies everywhere

Resources
Resources
Connect RISC-V computing and accelerate subsystems with silicon-proven interconnect IP. Unify protocols such as AMBA across 100’s of re-used IP blocks cutting complexity and maximizing resource efficiency. Derisk project schedules with leading system IP and expert support.
- EE Journal: Managing the Massive Data Throughput: AI-Based Designs and The Value of NoC Tiling
- EE Journal: The Network-on-Chip Pioneer: How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
- Electronic Design: All About NoCs
- SemiWiki: The Impact of Arteris on Automotive and Beyond with Frank Schirrmeister
- SemiWiki: A Broad View of Design Architectures and the Role of the NoC with Arteris’ Michal Siwinski
- EE Journal: The Freedom to Innovate: Arteris and the Rise of RISC-V
- SemiWiki: The Impact of Using a Physically Aware NoC with Charlie Janac
- Automating the Generation of Scalable and Reusable FMEDA in Complex Systems-on-Chip (SoCs)
- Building Better IP with RTL Architect NoC IP Physical Exploration
- Efficient Scaling of AI Accelerators Using NoC Tiling
- FMEDA Automation for Scalability and Reuse in Complex Systems on Chips (SoCs)
- Is the Missing Safety Ingredient in Automotive AI Traceability?
- Lessons Learned Integrating AI/ML Accelerators into Complex ISO 26262 Compliant Systems-on-Chip
- Safety Considerations for Network-on-Chip (NoC) Development
- The Role of Networks-on-Chips Enabling AI/ML Silicon and Systems
- Tiled Approach to System Scaling
- Magillem Registers – Automate the Hardware/Software Interface for Fast Chip Design
- Accelerating Timing Closure for Networks-on-Chip (NoCs) using Physical Awareness
- Optimizing Data Transport Architectures in RISC–V SoCs for AI/ML Applications
- FlexGen Product Tour
- Cache Coherency in Heterogeneous Systems
- Integration Challenges for RISC-V Designs
- Promises and Pitfalls of SoC Restructuring
- Scaling Performance in AI Systems
- Accelerate Time To Market With a First-Time Right Process
- Arteris FlexNoC 5 – Industry’s First Physically Aware Network-on-Chip IP
- How to Achieve Efficient Communication and Data Sharing in Multi-Core SoC Designs
- Revolutionizing SoC Performance with Network-on-Chip Technology
- Three Perspectives on System Design Challenges
- Making SoC Integration Simple – Achieve Higher Productivity and Quality
- A Configurable Test Infrastructure using a Mixed-Language and Mixed-Level IP Integration IP-XACT Flow
- A Design Flow for Critical Embedded Systems
- A Power Consumption Estimation Approach for Embedded Software Design using Trace Analysis
- AMS System-Level Verification and Validation using UVM in SystemC and SystemC-AMS: Automotive Use Cases
- Building a Portable Stimulus Flow Based on Magillem IP-XACT Packaging
- CodaCache: Helping to Break the Memory Wall
- Fundamentals of Semiconductor ISO 26262 Certification: People, Process and Product
- HW / SW Interface Generation Flow Based on Abstract Models of System Applications and Hardware Architectures
- Mobileye Case Study: Using Arteris for ADAS
- Power Dissipation of the Network-on-Chip in a System-on-Chip for MPEG-4 Video Encoding
- Re-Architecting SoCs for the AI Era
- Scalability – A Looming Problem in Safety Analysis
- Security in Artificial Intelligence
- Using Machine Learning for Characterizations of NoC Components
- Using Virtual Prototypes to Improve the Traceability of Critical Embedded Systems Flow
- Boost SoC Efficiency and Speed with FlexGen Smart NoC IP Automation White Paper
- Making Cache Coherent SoC Design Easier with Ncore
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