RISC-V and Arteris: Shaping the future of chip design
Unleashing innovation, simplifying connectivity, and driving a new era of specialized semiconductors with plug-and-play network-on-chip connectivity.
Overview
Freedom to innovate secure, smarter devices
RISC-V is reshaping semiconductor design with customizable, domain-specific architectures for AI, automotive, datacenter, and edge systems. But as SoCs scale, integrating processors, memory, and heterogeneous IP while ensuring system integrity and security can become a critical bottleneck.
Arteris addresses these challenges with network-on-chip (NoC) IP, SoC integration automation, and built-in hardware assurance capabilities. Together, these solutions enable faster, more predictable development of high-performance, secure RISC-V designs.
With over 20 years of expertise, Arteris helps engineering teams:
- Integrate RISC-V cores with diverse IP—seamlessly and at scale
- Automate SoC assembly, connectivity, and security policy enforcement
- Optimize performance, power, and area (PPA) across the interconnect
- Ensure interoperability across AMBA and emerging protocols
- Embed and verify hardware-level security by design
- Reduce risk and accelerate time-to-market
By combining advanced NoC IP, system-level automation, and hardware security verification, Arteris technology enables scalable, efficient, and production-ready RISC-V SoCs.
Advantages
Experience where it matters. Everywhere.
Seamless integration
Arteris network-on-chip technology helps ensure effortless RISC-V core integration with other IP blocks, making devices functional and efficient.
Expertise in connectivity
With over 20 years of experience, Arteris simplifies the complexities of inter-chip and intra-chip connectivity, enabling designers to focus on core innovation, while accelerating the design-to-market process.
Scalability
Arteris enables designers to create highly scalable ring, mesh, and torus topologies and edit generated topologies, in contrast to black box compiler approaches. This optimizes each individual network router.
The Damo Wujian Alliance, spearheaded by Damo Academy (an affiliate of Alibaba Group), is an ecosystem alliance driving the adoption and development of the RISC-V instruction-set architecture. The coalition focuses on high-performance system-on-chip (SoC) designs, particularly in edge AI computing. As part of the alliance, Arteris plays a pivotal role by enabling the integration of Damo Academy’s / T-Head’s Xuantie RISC-V processor IP cores with its Ncore cache coherent NoC system IP, resulting in efficient data transport architectures within cores and between chips, enabling cutting-edge applications in AI, machine learning, and more.
Design for next-gen demands with Ncore Cache Coherent NoC IP
Ncore is the only scalable, highly configurable, ISO 26262 certified cache coherent NoC for modern SoC designs.
- Any processor
- Multiple protocols
- Flexible configuration
Maximize engineering productivity and accelerate time-to-market with Ncore. Our white paper shows how you could save 50+ person years over a DIY project.
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Resources
Connect RISC-V computing and accelerate subsystems with silicon-proven interconnect IP. Unify protocols such as AMBA across 100’s of re-used IP blocks cutting complexity and maximizing resource efficiency. Derisk project schedules with leading system IP and expert support.
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