Designers have many paths for differentiating RISC-V solutions. One path launches into various RISC-V core customizations and extensions per the specification. Another focuses on selecting and assembling IP blocks in a complete system-on-chip (SoC) design around one or more RISC-V cores. A third is emerging: interconnecting RISC-V cores and other IP blocks with a network-on-chip (NoC) instead of a simple bus structure. And it’s not just at the high end – pairing RISC-V cores with NoCs answers many SoC design challenges where data must flow efficiently in any workload using any on-chip protocol.

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