High-end integrated circuit (IC) designs are becoming increasingly complex. A system-on-chip (SoC) device can contain hundreds of intellectual property (IP) blocks, each of which may represent millions of transistors. It is not uncommon these days for even small startup companies to create multi-billion transistor devices.

The number of transistors may be the least of the design team’s challenges. There are also interfaces and protocols coupled with buses, crossbar switches, or a network-on-chip (NoC) interconnect that link the IPs together. Furthermore, today’s IPs tend to be extremely configurable. A single IP may contain hundreds of thousands of control and status registers (CSRs), and the entire SoC can have millions of these registers.

Predictably, managing designs of this capacity and complexity has grown increasingly involved. In many cases, teams are spread across multiple locations, but organizations often have limited cross-team synergy despite the need to collaborate. The complexities of integrating content from various sources, such as third-party, internally developed and legacy IPs, which can all be highly configurable, are compounded by inconsistent data and documentation. As a result, problems often manifest themselves deep in the product development cycle, at the hardware-to-hardware boundaries between IPs and the hardware-to-software interfaces between the platform and its applications.

Many existing design flows require some operations to be performed by hand across numerous tasks and electronic design automation (EDA) tools. For example, tasks such as creating makefiles and scripts to automate different process steps, like compilation and simulation or RTL synthesis and formal verification, often require manual intervention.

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