What is a NoC interconnect?
A network‑on‑chip (NoC) interconnect is a scalable, packet‑based communication fabric that replaces traditional hierarchical bus or crossbar architectures in complex systems‑on‑chip (SoCs). As SoCs grow and transistor nodes shrink, routing density, timing budgets and quality‑of‑service (QoS) demands make legacy interconnect structures unmanageable. NoC technology is often called “a front‑end solution to a back‑end problem,” because it addresses physical design challenges through an architectural shift.
Why modern SoCs need NoC technology
- Reduce wire routing congestion.
- Ease timing closure.
- Achieve higher operating frequencies.
- Change IP easily for derivative chips.
Coherent and non‑coherent NoC interconnects
NoC interconnects may be coherent or non‑coherent. Coherent NoCs help ensure data consistency across processor caches, while non‑coherent NoCs rely on software‑managed synchronization. Understanding these approaches is essential to optimizing performance, power efficiency, and data integrity across heterogeneous SoCs.
Reduce wire routing congestion
Arteris NoC fabrics help reduce the number of global wires required to route data throughout the SoC. Packetization, narrowing wide buses, and distributed routing dramatically cuts wiring congestion, which is one of the leading causes of backend delays as IP counts continue to increase.
Ease timing closure
The distributed nature of Arteris NoCs allows architects to place pipeline registers, or register slices, at precise points along interconnect paths. This helps resolve long‑path timing issues without affecting neighboring modules. Localized timing control enables predictable timing closure across the chip.
Achieve higher operating frequencies
NoC architectures simplify routing and switching logic, enabling SoCs to operate at higher clock frequencies than multilayer bus or crossbar designs. Pipeline registers can be placed anywhere along a connection to meet frequency targets with minimal added latency.
In addition, globally asynchronous locally synchronous (GALS) support enables IP blocks with independent local clocks to communicate reliably across asynchronous boundaries, improving system‑wide frequency scalability.
Change IP easily for derivative chips
Arteris NoC interconnects are protocol agnostic, with transaction, transport, and physical layers decoupled. Small network interface units (NIUs) convert each IP’s protocol transactions into packetized data. This allows architects to replace or update IP blocks without modifying the entire interconnect fabric, accelerating derivative chip development and ECO cycles.
Ncore coherent NoC interconnect
A coherent NoC interconnect manages cache‑to‑cache communication and helps ensure that all processors view shared memory consistently. Arteris Ncore implements cache coherence using MOESI state management and directory‑based tracking mechanisms.
Key features of a coherent NoC
- Implements MOESI cache protocol to maintain consistency across local caches.
- Uses directory‑based mechanisms to track shared data states.
- Optimized for low‑latency, high‑bandwidth cache‑to‑cache transfers.
When to use coherent NoC
- Multicore processors requiring shared memory models.
- Real‑time applications where deterministic data consistency is essential.
FlexGen, FlexNoC and FlexWay non‑coherent NoC interconnects
Non‑coherent NoC interconnects do not maintain cache coherence across the system. Each core manages its own local cache, and software ensures consistency when necessary. This approach helps reduce hardware complexity and power consumption, and is ideal for workloads with minimal intercore data sharing.
Key features of a non‑coherent NoC
- Lower power consumption due to reduced hardware complexity.
- Simple integration for IPs with minimal shared‑memory interaction.
When to use a non‑coherent NoC
- Single‑core or lightly interconnected multicore systems.
- Applications with predictable data‑sharing patterns manageable by software.
Combining coherent and non‑coherent NoCs
Modern SoCs often combine coherent and non‑coherent NoCs to optimize performance, power, and architectural efficiency. Coherent NoCs support CPU clusters and high‑performance accelerators, while non‑coherent fabrics connect peripherals and subsystems with limited data‑sharing needs.
Best practices
- Use coherent NoCs for data‑intensive processing clusters.
- Use non‑coherent NoCs for peripherals or accelerators with minimal shared‑memory requirements.
- Tailor NoC coherence strategy to the application domain’s performance and consistency requirements.
In summary
Coherent and non‑coherent NoC interconnects provide complementary strengths for modern SoC design. By combining protocol‑agnostic fabrics, flexible timing strategies and advanced cache‑coherency mechanisms, Arteris NoC technology enables scalable, high‑performance and energy‑efficient architectures tailored to specific workload needs.
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Arteris FlexGen Interconnect IP
