What is network-on-chip (NoC) technology?

NoC technology is a scalable, packet-based communication fabric used to connect processing elements, memories, and peripherals within complex system-on-chip (SoC) designs. As semiconductor nodes shrink and SoCs integrate more IP blocks, traditional hierarchical buses and crossbars can create severe routing congestion, timing challenges, and quality-of-service (QoS) limitations.

NoC technology is often described as “a front-end solution to a back-end problem,” because it addresses physical design issues, such as wiring density and timing closure, through architectural improvements at the front end of the design process. What once behaved like a small village road system now resembles a multilane freeway network, requiring advanced traffic management.

Key characteristics of NoC technology

Arteris NoC technology implements several advanced architectural features that help improve scalability, performance, and physical design convergence across modern SoCs.

Separation of transaction, transport, and physical layers

Unlike monolithic bus-based approaches, NoC architectures separate the transaction, transport, and physical layers. This modular structure allows designers to update protocols, optimize routing paths, or adjust link characteristics without disrupting the overall interconnect. Layer decoupling also makes it easier to implement advanced features like QoS, power domains, clock domains, and security.

Packetization of data

NoC fabrics packetize data into structured units, enabling flexible serialization and variable bit‑widths. Packetization helps reduce the need for wide, parallel buses, and alleviate global routing congestion. It also supports multiple transport modes, bandwidth allocation schemes, and QoS mechanisms within shared interconnect resources.

Support for any transaction protocol

Arteris NoC products support Arm AMBA protocols, OCP, and other proprietary interfaces. Small network interface units (NIUs) translate each IP’s protocol-specific transactions into packet-based traffic. This protocol-agnostic approach allows designers to integrate legacy IP, mix protocol families, and scale across multiple product generations without redesigning the entire interconnect.

In summary

NoC technology provides a flexible, scalable, and future-proof foundation for modern SoC designs. By separating architectural layers, packetizing data and supporting multiple protocols, Arteris NoC technology addresses routing congestion, timing closure, and integration challenges that traditional bus architectures can no longer handle.

Learn more and explore Arteris solutions

Arteris FlexNoC Interconnect IP

Arteris FlexGen Interconnect IP

Arteris FlexWay Interconnect IP

The Arteris interconnect IP offers us a convenient solution to handle the high speed communication needed between our SoC and external modem IC. Our customers will benefit from the lower BOM cost and power consumption as a result of this IP. We look forward to Arteris’ interconnect IP helping us shorten development schedules and lower risks associated with compatibility.
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Thomas Kim
Vice President, SoC Platform Development, System LSI, Samsung Electronics