Overview
Packetization and serialization are core requirements of any network‑on‑chip (NoC) architecture. Packet‑based communication enables flexible bit‑width scaling, predictable timing, reduced wiring, and improved routing efficiency. Arteris NoC technology uses packetized transport, variable‑width serialization, and distributed network interface units (NIUs) to deliver high‑bandwidth, low‑latency, and physically optimized SoC interconnects.
Packetization
In an Arteris NoC, network interface units (NIUs) convert traditional AMBA, OCP, and proprietary protocol transactions into packets suitable for transport across the interconnect. This abstraction allows each IP block to communicate using its native protocol, while the NoC handles routing, switching, and flow control.
At the edges of the network, NIUs connect to IP blocks through standard or custom socket interfaces, helping to ensure broad compatibility and simplifying integration. Packetization enables consistent handling of transactions across diverse protocols, supports QoS policies, and forms the foundation for scalable serialization and traffic shaping.
Serialization
Serialization determines how packet data is transmitted across NoC links using different bit‑widths. Flexible serialization allows the interconnect to adapt to physical distance, bandwidth requirements, and available routing resources. By serializing packets, the NoC significantly reduces wire count compared to wide, parallel buses, helping to improve physical convergence and simplify back-end routing.
Physical transport links
The physical layer defines how packets travel between NoC units. Arteris supports multiple link types, including standard transport links, globally asynchronous / locally synchronous (GALS) links for long‑distance or cross‑domain communication, and chip‑to‑chip links for multi‑die systems. Each link type can be optimized independently without modifying transaction or transport behavior.
Benefits of separate transaction and transport layers
Arteris NoC architectures maintain clear separation between transaction, transport, and physical layers. This allows link characteristics and serialization widths to be modified without impacting higher‑level protocol handling. Point‑to‑point connections eliminate high‑fanout nets, improving timing predictability and routing efficiency.
Efficient NoC implementation with NIUs
Since the majority of interconnect logic resides inside NIUs located close to their respective IP blocks, the transport fabric itself remains lightweight. This reduces gate count, eases placement and routing, and enables fully pipelinable paths across the NoC. Fewer global wires and localized logic help the design achieve high operating frequencies and faster timing closure.
In summary
Packetization and serialization are fundamental to scalable NoC design. Arteris NoC technology uses packet‑based communication, flexible serialization depths, multi‑mode physical links and NIU‑centric integration to help reduce wiring, improve timing, support protocol diversity, and enable efficient multi‑domain SoC architectures.
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Arteris FlexNoC Interconnect IP
