Overview
Modern systems‑on‑chip (SoCs) rely on advanced power‑management techniques to balance energy efficiency, thermal constraints, and workload‑driven performance demands. Arteris network‑on‑chip (NoC) technology supports dynamic voltage and frequency scaling (DVFS), multidomain clocking, power partitioning and intelligent gating strategies to optimize system‑wide power usage, while preserving predictable latency and throughput.
Clock, voltage, and frequency domains
Arteris NoC and accompanying design tools allow architects to define and validate multiple independent clock, voltage, and frequency domains. These domains can operate at different performance points and dynamically adjust their voltage and frequency levels through DVFS based on real‑time workload conditions. This enables fine‑grained power control across CPU clusters, accelerators, memory subsystems. and peripheral IPs.
Clock gating
Dynamic clock gating helps ensure NoC components are clocked only when they are actively processing traffic, reducing dynamic power consumption. A configurable clock manager supports flexible clock and reset policies tailored to each subsystem.
Power‑domain partitioning is enabled by integrated controllers, socket‑level disconnect protocols and dedicated error‑handling IP. Arteris NoC automatically inserts asynchronous clock crossings and level shifters between voltage domains to maintain correct operation without user intervention.
GALS: Globally asynchronous, locally synchronous operation
GALS technology allows subsystems with independent local clocks to communicate across asynchronous boundaries. Arteris NoC technology implements compact, unidirectional bi‑synchronous FIFOs that provide low‑latency transfer without handshake overhead. GALS boundaries can be inserted along any NoC link, giving designers flexibility to meet timing, frequency, and floor-planning constraints.
When a subsystem must retain state while powered down, retention registers preserve critical data. Electrical isolation layers and socket‑disconnect mechanisms cleanly separate domains when power is gated.
Power intent using CPF and UPF
Arteris NoC captures and exports power intent through industry‑standard formats, including the Common Power Format (CPF) and Unified Power Format (UPF). These specifications formalize definitions for power domains, isolation strategies, level shifting, retention behavior, and shutdown control, helping to ensure consistency from architectural design through implementation and verification.
In summary
Arteris NoC technology provides a robust foundation for low‑power, high‑efficiency SoC designs. DVFS, clock gating, asynchronous clock crossings, domain isolation, and CPF/UPF‑based power intent work together to deliver scalable performance, while minimizing energy consumption across heterogeneous processing elements.
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Arteris FlexNoC Interconnect IP
