What is a NoC interconnect?
A network-on-chip (NoC) interconnect is a scalable, packet-based communication fabric designed to replace traditional hierarchical bus and crossbar architectures in complex systems-on-chip (SoCs). As transistor dimensions shrink and SoCs integrate more IP blocks, traditional interconnect approaches create wiring bottlenecks, timing challenges, and quality-of-service (Qos) limitations. NoC technology is often described as “a front-end solution to a back-end problem,” because it addresses physical design issues at the architectural level, including routing congestion and timing closure.Why today’s SoCs need NoC technology
- Reduce wire routing congestion.
- Ease timing closure.
- Achieve higher operating frequencies.
- Enable easier IP changes and derivative chip creation.
Reduce wire routing congestion
Arteris NoC interconnect technology significantly reduces the number of wires required to move data throughout the SoC. By packetizing data and eliminating large parallel buses, NoCs reduce global routing resources and alleviate congestion. This is especially critical as the number of IP blocks increases and traditional bus structures become unmanageable.Ease timing closure
The distributed architecture of Arteris NoC fabrics allows architects to insert pipeline registers, also known as register slices, exactly where they are needed to meet timing. These pipelines break up long critical paths without negatively affecting timing in nearby IP blocks. This capability helps makes timing closure more predictable and efficient across the chip.
Achieve higher operating frequencies
Compared to multilayer bus or crossbar architectures, NoC interconnects simplify switching and routing logic, enabling higher operating frequencies. Fine-grained pipeline placement allows long or speed-sensitive paths to meet frequency targets with minimal latency penalties.
Support for globally asynchronous locally synchronous (GALS) architectures allows modules with independent clocks to communicate across asynchronous boundaries, improving overall SoC performance and clocking flexibility.
Change IP easily for derivative chips
Arteris NoC technology makes it easier to replace or update IP blocks during SoC development because the interconnect is protocol agnostic. The transaction layer is separated from the transport and physical layers.
Small network interface units (NIUs) translate each IP’s protocol into packetized data. With NIUs located near initiator and target IP blocks, the rest of the NoC remains composed of simpler routing and switching components. This reduces rework and accelerates derivative chip creation.
In summary
NoC technology provides critical advantages for scaling modern SoCs. By reducing global wiring, easing timing closure, supporting higher operating frequencies and simplifying IP integration, NoCs deliver a flexible, high-performance communication backbone for today’s heterogeneous, multi-core and multi-die systems.
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