Overview
Routing congestion is one of the most persistent physical design challenges in advanced system-on-chip (SoC) architectures. As SoCs scale to hundreds of IP blocks, high-speed interfaces, and dense memory subsystems, the sheer number of wires required to move data across the chip often exceeds available routing resources. Arteris network-on-chip (NoC) interconnect IP addresses this challenge at the architectural stage to help reduce wire count, ease backend implementation, and improve timing closure.
What is routing congestion?
Routing congestion occurs when too many wires must be routed through limited physical space on a chip. Since the interconnect fabric lives in the “white space” between IP blocks, the number, width, and spacing of wires determine how easily the backend tools can complete routing.
Signal wires used for data transport are especially vulnerable to congestion. Power and clock wires occupy upper metal layers with tall, wide metal traces. This forces signal wires down into mid- and lower-metal layers, where wire width, spacing constraints, and resistance are more restrictive.
Metal layers and number with each process node advance
Source: C. J. Alpert and G. E. Tellez, “The Importance of Routing Congestion Analysis”, DAC47
Measuring congestion: g-cells
EDA tools divide the floorplan into grid cells known as g-cells (or bins). Each g-cell can accommodate only a finite number of wires. Congestion is expressed as a ratio:
- 1.0 = 100% congested
- 0.5 = 50% congested
A g-cell becomes congested when required wire area exceeds what the cell can physically support. This includes metal width, spacing, and dielectric isolation to prevent crosstalk and signal integrity issues. Congestion is most common near:
- DRAM memory controllers
- I/O pads and pin clusters
- High-traffic IP blocks
Root causes of routing congestion
Shrinking transistors enable more IP blocks and features per generation, but wire scaling lags far behind transistor scaling. As a result, more IP leads to exponentially more wires
The number of required wires grows approximately with the square of transistor count. This leads to wire demand far outpacing available routing resources.
Wires do not scale like transistors
Wire resistance per unit length doubles each process generation, while capacitance remains nearly constant. Even as transistors switch faster, long-distance wires increasingly dominate delay.
Metal layers do not scale down proportionally to transistor scaling
Source: Saxena, Prashant, Shelar, Rupesh S., Sapatnekar, Sachin, “Routing Congestion in VLSI Circuits,” Springer, 2007.
Wire spacing increases at advanced nodes
Higher switching frequencies require wider spacing between wires to prevent crosstalk and noise. This reduces available routing tracks and increases congestion.
Metal layers expand, but floorplan white space remains fixed
Advanced nodes add more metal layers, but that does not offset the rising wire demand in modern SoCs.
RC delay and wire scaling limitations
Since wire RC delay does not improve with shrinking geometries, long interconnect paths consume disproportionate timing budget. Routing congestion worsens this by forcing detours:
- Longer distances → higher resistance
- Lower metal layers → more delay
- Indirect paths → increased power and timing uncertainty
As congestion grows, EDA tools reroute wires around blocked g-cells, further increasing delay, skew, and timing closure difficulty.
How to eliminate routing congestion
The most effective way to eliminate routing congestion is to eliminate wires at the RTL/architecture level. Fixing congestion early provides exponential benefits later in the backend flow.
The traditional OCP crossbar on the left has pronounced routing congestion. The same IP with fewer wires due to use of Arteris FlexGen®, FlexNoC® or FlexWay® interconnect IP has no routing congestion. The protocols are OCP for both.
Source: Arteris customer design.
NoC is a front-end solution to a back-end problem
Arteris FlexGen, FlexNoC and FlexWay interconnect reduces wire count by up to 50% compared to traditional multilayer bus or crossbar architectures. Instead of hundreds of point-to-point connections, the NoC packetizes data and routes it over shared, optimized paths.
Benefits of reducing wires early include:
- Fewer ECO loops
- Shorter timing closure cycles
- Less routing detouring
- Lower dynamic power due to shorter wires
- More predictable backend convergence
Advantages of Arteris NoC over traditional interconnects
Arteris reduces routing congestion and improves physical convergence through:
- Configurable link widths matched to IP bandwidth
- Separation of transaction and transport layers (easy IP change-out)
- Fine-grained pipeline insertion for timing closure
- Automatically generated, physically aware NoC topologies
- GUI + scripting for rapid design iteration
- Automated QoS, serialization, and clock/power domain management
Arteris FlexGen, FlexNoC and FlexWay and wire reduction
Across medium and large SoCs, Arteris NoC technology typically requires half the wires of an AMBA bus or crossbar. With fewer wires and smaller distributed elements, the NoC:
- Cuts routing congestion
- Enables higher operating frequencies
- Reduces power and area
- Simplifies IP integration and late-cycle changes
Arteris configuration and synthesis tools allow designers to create, simulate, export RTL, and iterate quickly, even across hundreds of IP blocks.
In summary
Wire routing congestion is a fundamental limiter of SoC performance, power, and schedule predictability. As wires do not scale with transistors, architectural solutions rather than back-end workarounds are essential.
Arteris NoC interconnect IP dramatically reduces wire count, improves timing closure, and enables efficient routing across increasingly complex SoCs. By addressing congestion at the source, Arteris provides a robust, scalable foundation for next-generation chips in automotive, AI, mobile, and high-performance compute markets.
Learn more and explore Arteris solutions
Arteris FlexGen Interconnect IP
