Overview
Simulation and modeling are critical for evaluating performance, validating architectural choices, and reducing development cycles in complex systems‑on‑chip (SoCs). Arteris FlexExplorer uses automatically generated Accellera SystemC TLM 2.x models to simulate specific FlexNoC interconnect configurations, enabling rapid scenario‑based exploration and early design optimization.
Simulation and modeling with FlexExplorer
Arteris FlexNoC, FlexGen and FlexWay SystemC TLM models are automatically generated based on the user’s interconnect configuration. These models integrate directly into the FlexExplorer environment, where architects can perform script‑based or interactive performance evaluation. Associated IP‑XACT descriptions help ensure consistent integration across EDA tool flows.
Models can also be exported for use in third‑party, system‑level modeling suites, such as Synopsys Platform Architect. Arteris provides three abstraction levels:
- Programmer’s View (PV)
- Architectural View (AV)
- Verification View (VV)
These views support fast exploration, timing analysis, and cycle‑accurate verification.
PV models (TLM 2.x LT)
PV models are derived from the interconnect specification level. They capture functional behavior, including address decoding, transaction splitting, security checks, and ordering constraints. PV models support TLM 2.x loosely‑timed (LT) execution, including blocking transport, debug interfaces, and direct memory interface (DMI) extensions.
AV models (TLM 2.x AT)
AV models are derived from the FlexNoC architecture level. They extend the functionality of the PV model by modeling packet routing, topology, transaction context limitations, serialization, clocking and pipeline stages, buffering, and arbitration policies. These TLM 2.x approximately‑timed (AT) models capture timing behavior more precisely, supporting architectural tradeoff studies and congestion analysis.
VV models (TLM 2.x CA)
VV models reflect the structure and timing of the RTL‑level interconnect. These cycle‑accurate (CA) models provide the highest fidelity and can include transactor‑based or pin‑level interfaces. VV models are ideal for validating that functional behavior, latency paths, and microarchitectural features match RTL expectations.
In summary
Arteris FlexExplorer and its SystemC TLM 2.x model suite provide a powerful framework for early NoC performance exploration, architectural evaluation, and verification. With PV, AV, and VV layers of abstraction, designers can rapidly iterate, analyze timing and validate cycle‑accurate behavior across all stages of system development.
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Arteris FlexNoC Interconnect IP
