AMBA CHI, ACE, ACE‑Lite, AXI, AHB, APB and OCP transaction protocols

Overview

Arteris network‑on‑chip (NoC) technology provides a flexible, scalable interconnect architecture that supports all major industry‑standard transaction protocols, including AMBA CHI, ACE, ACE‑Lite, AXI, AHB, APB and OCP.

This flexibility enables seamless integration of heterogeneous IP blocks and supports both coherent and non‑coherent subsystems within the same system-on-chip (SoC).

Modern SoC designs frequently combine coherent NoCs for CPU clusters and accelerators with non‑coherent NoCs for peripheral subsystems. Arteris solutions enable this hybrid architecture without the routing congestion, protocol constraints or structural rigidity found in traditional interconnect approaches.

Coherent and non‑coherent NoC integration

Arteris technology allows designers to combine coherent and non‑coherent interconnect fabrics within the same SoC. Coherent NoCs maintain system‑wide data consistency for multi‑core and accelerator subsystems, while non‑coherent fabrics support peripherals and IP blocks that do not require hardware‑managed cache coherence.

FlexNoC non‑coherent NoC interconnect

Arteris FlexNoC provides a scalable, packet‑based transport layer optimized for non‑coherent data movement. It enables multi‑clock, multi‑voltage operation, configurable data widths and fine‑grained QoS controls, which all contribute to efficient SoC integration and predictable performance.

Ncore cache coherent NoC interconnect

Arteris Ncore delivers hardware cache coherence for systems that require low‑latency data sharing, such as multi‑core CPUs, GPU clusters, real‑time accelerators and AI engines. It supports AMBA CHI, ACE and ACE‑Lite and provides directory‑based snoop filtering and scalable coherency mechanisms.

Supported transaction protocols

Arteris NoC IP provides native support for AMBA CHI, AMBA 5 ACE, AMBA 5 ACE-Lite, AMBA 5 ACE-Lite+DVM, AXI, AXI4, AXI5, AHB, and APB, as well as OCP where required. This enables IP reuse across product families and simplifies platform‑based design methodologies.

Limitations of traditional bus and crossbar interconnects

In legacy bus or crossbar architectures, changing an IP block often requires cascading modifications across the physical topology, with wider buses, altered switching structures, new width, protocol and clock domain bridges, and additional timing work. Even a simple derivative SoC may require significant backend redesign, impacting schedule and verification cost.

These monolithic interconnect structures create routing congestion, limit clock‑domain flexibility and increase power consumption due to long global wires and unscalable bus widths.

Network interface units enable seamless protocol adaptation

Arteris NoC technology isolates transaction protocol handling inside compact network interface units (NIUs). Each NIU performs protocol conversion, packetization and serialization close to the associated IP block. This architecture enables:

• IP‑level protocol independence
• Easy integration of new or replacement IP blocks
• Mixed data widths and mixed clock rates
• Reduced placement and routing congestion

Since NIUs handle protocol differences, the underlying transport fabric remains unchanged, even when IP blocks are swapped or upgraded.

Comparison to traditional crossbar architectures

Unlike crossbars, which rely on centralized switching structures placed between IP blocks, Arteris NoC interconnects distribute routing resources throughout the chip. This helps eliminate choke points and reduce the tangle of global wires that typically cause congestion and timing issues.

The packet‑based transport layer allows multiple protocols to be supported concurrently without specialized bridge logic or topology restructuring.

In summary

Arteris NoC technology provides comprehensive support for AMBA CHI, ACE, ACE-Lite, AXI, AHB, APB, and OCP transaction protocols, enabling seamless integration of heterogeneous IP across both coherent and non-coherent subsystems. By isolating protocol handling inside compact NIUs, Arteris allows designers to mix protocols, clock domains, data widths, and power domains without modifying the underlying transport fabric. This NIU-based adaptation eliminates the routing congestion, timing complexity, and rigidity of traditional bus and crossbar architectures, making it dramatically easier to create derivative SoCs, replace IP blocks, and scale performance across multi-die and chiplet-based designs.