AMBA CHI, ACE, ACE-Lite, AXI, AHB, APB, OCP Transaction Protocols


AMBA CHI*, ACE*, ACE-Lite, AXI, AHB, APB, OCP** Transaction Protocols

Arteris network on chip (NoC) technology is the most flexible interconnect technology because one can use any socket protocol, any architecture, and any combination of clock and power domains.

Modern SoC designs combine both coherent and non-coherent NoC interconnects to leverage the strengths of each approach. For instance, a system might use a coherent NoC for the core processing cluster where high-performance and data consistency among cores are critical, while employing non-coherent interconnects for peripheral modules or specialized processing units where data sharing is minimal or can be managed at the software level.

FlexNoC Non-Coherent NoC Interconnect

FlexNoC diagram

Ncore Cache Coherent NoC Interconnect

Ncore diagram

Arteris network on chip technology includes out-of-the-box support for AMBA 4 ACE, AXI, AXI4, AHB, APB, and ACE-Lite protocols.

With today’s platform based SoC design methodologies, it is important for design teams to be able to quickly generate derivatives based on a single SoC platform. These derivatives usually require changing IP blocks that use a different protocol configuration, or even an entirely different protocol, than the original IP blocks.

In traditional bus and crossbar interconnects, changing an IP block means not only dealing with a different transaction protocol, but also making changes to the path widths and physical bus topology to accommodate the new IP. At a minimum, bridging is usually required. In the worst case, changing IP blocks leads to back-end timing and physical placement issues that delay the release of what was promised as a “simple derivative.”

In comparison, changing an IP block on a NoC interconnect only requires changing the configuration of the network interface unit (NIU) to accommodate the protocol and bit width changes for that IP block. The NoC interconnect’s packet-based transport allows mixing data widths and clock rates.

Protocol conversion, packetization and serialization are performed in the network interface units (NIU), which are physically located close to each NIU’s corresponding IP block and do not create placement and routing issues.

This is in direct contrast to a traditional bus or crossbar approach where the interconnect at the physical stage is a monolithic switch or series of switches that must be squeezed between existing IP blocks, along with the commensurate tangle of congested wires.

** FlexNoC and FlexWay only
* Ncore only

FlexNoC’s power management features and low latency helped us create the lowest-power IoT communication devices in the world. Just as important were the business benefits: Using FlexNoC allowed us to create a small set of digital logic SoC dies that serve as the brains of more than one hundred different products, each customized for its particular market.

FlexNoC’s flexibility and automation, combined with our implementation of software-programmable on-chip firewalls and power disconnect features, enabled us to produce an entire product line with a minimal number of digital logic components.

Oyvind Birkenes, General Manager, Wireless Connectivity Solutions, Texas Instruments

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Arteris FlexNoC 5 Physically Aware Network-on-Chip IP

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