Semiconductor Engineering: Many Chiplet Challenges Ahead

Madelyn Miller, Apr 14, 2021

Assembling systems from physical IP is gaining mindshare, but there are technical, business and logistical issues that need to be resolved before this will work.

Michael Frank, fellow and system architect at Arteris, is quoted in this new Semiconductor Engineering article.

Advanced packaging is seen as the most likely path to keep Moore’s Law going, but there are several challenges that have yet to be overcome — and several lurking pitfalls for the unaware. Some of these are technical, some business, and other just because the necessary skills are distributed today, meaning that there could be knowledge gaps created by silos.

Much of the emphasis so far has been on functionality, including how designs should be partitioned and how to logically stitch them back together. The bulk of this work has shown up in products from several vertically integrated companies, which often have applied their traditional tool chain when conducting the necessary analysis. But that only works when you have complete access to all pieces of the design, which is why IDMs have been the first out of the gate with chiplets.

To read the entire SemiEngineering article, please click here.

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