Blog Home Blog Search: Date EDN: Network-on-chip (NoC) interconnect topologies explained Today’s complex system-on-chip (SoC) designs can contain between tens to hundreds of IP blocks... July 27, 2023 Continue Reading SemiWiki: Back to Basics – Designing Out PPA Risk I wrote earlier about managing service-level risk in SoC design, since the minimum service level a system can guarantee under realistic traffic is critical to OEM guarantees... July 20, 2023 Continue Reading EDACafé: Automating System-on-Chip Integration for the 21st Century Today’s multi-billion-transistor system-on-chip (SoC) devices are composed of hundreds of functional intellectual property (IP) blocks. The creation of SoCs is typically... July 20, 2023 Continue Reading Semiconductor Engineering: Megatrends At DAC Spotting key trends over three days of a semiconductor design conference is a challenge, but some important ones come into focus after attending multiple sessions — AI/ML, chiplet... July 19, 2023 Continue Reading Semiconductor Engineering: The Design Automation Conference Turns 60! What’s Hot? What’s Next? This coming week from July 9th to July 13th, experts from all over the world will descend on the Moscone Center in San Francisco... July 7, 2023 Continue Reading Design & Reuse: Push-Button NoCs for SoCs Today's system-on-chip (SoC) devices may be composed of hundreds of functional blocks known as intellectual property (IP) blocks. Each of these IPs can contain hundreds of millions of transistors.... July 4, 2023 Continue Reading « Previous Page 1 … 6 7 8 9 10 … 58 Next Page » Arteris Articles News and original writing about on-chip interconnects, on-chip communications and the semiconductor intellectual property industry. Subscribe to Arteris News