Advanced Quality of Service
End-to-end Quality of Service (QoS) is included with the FlexNoC interconnect product and is designed to ensure all on-chip data flows can concurrently meet latency and bandwidth requirements while sharing the finite bandwidth of DDR memory.
The key to success is end-to-end quality of service, all the way from master initiation through memory and back. Arteris implements end-to-end QoS through the interconnect and the FlexMem Multi-Array Memory Scheduler, which is tightly coupled to the NoC interconnect.
Heterogeneous Traffic Types
Each IP block in an SoC has different characteristics that affect the system from a performance perspective: Protocol, clock frequency, data width, peak throughput, data traffic patterns (transaction lengths, address alignments, regularity, etc.), and reactions to latency or transient back pressure.
For example, the following initiators have very different performance profiles and latency and bandwidth requirements:
|CPU||Latency sensitive||Processing stops for many cycles when there is a cache miss.|
|Video Display||Real time & latency critical||The video display subsystem’s buffer must never be empty or the end-user will see black pixels.|
|Imaging System||Real time & bandwidth sensitive||The imaging system operates on several frames in advance and is able to adjust its output quality.|
|Background File Download||Best effort||File downloads can be stalled without compromising the end user’s experience.|
Arbitration: Dynamic Packet Priorities & Dynamic Pressure Propagation
Arteris Network on Chip technology addresses these varied QoS needs in many ways: First, the interconnect assigns priorities to transactions to ensure they arrive at the target in the proper order to meet system requirements. Priority levels can be attached to individual packets or to all transactions pending on a socket. The interconnect can also assign Dynamic Packet Priorities at runtime.
Second, the interconnect can sense when high priority packets may be blocked or slowed due to downstream traffic congestion and can then clear a path for these high priority packets. This technology, called Dynamic Pressure Propagation, is analogous to a fire truck racing down city streets: All traffic pulls to the side of the road to let the fire truck through.
Bandwidth Limiters and Rate Regulators
Many times architects will want to implement QoS within their SoC but the QoS prioritization data is not available from the individual IP blocks. In this case, QoS information may be generated from within the NoC interconnect using Arteris’ QoS Generator. The QoS Generator can instantiate sophisticated, and software programmable, means to regulate interconnect QoS, including:
- Bandwidth Limiters – Bandwidth limiters cause a socket to stop accepting requests when a run-time programmable throughput threshold has been exceeded.
- Rate Regulators – Rate regulators cause a socket’s transactions to be demoted when a bandwidth threshold is reached. This can be considered a smoother version of the bandwidth limiter because transactions are only demoted instead of stalled.
The Arteris FlexMem Multi-Array Memory Scheduler is an integral part of Arteris’ end-to-end quality of service (QoS). This memory scheduler is intended to connect to any DRAM controller front-end, such as those from Cadence (Denali), Synopsys (Virage Logic), Uniquify. It provides optimal scheduling and arbitration to ensure the maximum possible utilization of DRAM memory. Its features are tuned to the capabilities of the Arteris FlexNoC interconnect.
Using the Arteris FlexMem Multi-Array Memory Scheduler reduces routing congestion because it, along with the FlexNoC interconnect, consists of a distributed architecture of small RTL components. It is also very flexible, with the architect being able to choose custom numbers of ports and array sizes to meet system requirements. The end result is a tuned memory scheduler that is simpler to implement in physical design, with less routing congestion around the memory controller than existing solutions.
The FlexMem scheduler is also more efficient than other scheduling solutions, because many features such as burst splitting, clock conversion, serialization conversion and flow rate adaptation are accomplished upstream of the scheduler in the FlexNoC interconnect’s distributed architecture.
The FlexMem Memory Scheduler is tightly integrated with Arteris’ End-to-End QoS, implementing multistage arbitration and features such as Dynamic Packet Priorities and Dynamics Pressure Propagation.
We exhaustively benchmarked the Arteris NoC interconnect IP against the competition. We need real-time performance with extremely low latency between video IP blocks, and we found the Arteris NoC to be the best solution for EyeQ3. Furthermore, we found Arteris’ memory scheduler to be superior, with excellent Quality of Service in a smaller die area. With Arteris, our customers can be assured of responsiveness and reliability to help reduce collisions and make roads safer.
Elchanan Rushinek, Vice President of Engineering, Mobileye