SoC Integration Products

Magillem™️ Connectivity

Magillem Connectivity

Benefits

Features

Continuous integration: With a robust SoC build process that adapts safely and quickly to changes. Automated build, assembly and check flow reducing tedious time-consuming tasks.
Productivity: Get all product teams on the same development platform. Replace ad-hoc scripts, local know-how, and empower true innovation. Shorten and streamline the integration process, accelerating connectivity through automation.
Manage risk: Reliable scalability for larger designs, and derivatives demanding a shorter schedule. Built-in checkers for higher-quality designs with correct by-construction IP-XACT description.

Industry-proven platform for SoC integration based on widely adopted standard to build and manage connectivity.
A set of predefined automated operations to easily connect, configure IPs through the hierarchy, and handle components (move, merge, flat, insert...).
On-the-fly, create files to drive physical design and verification, software interface connecting hardware to the software stack.
Readily integrate into your design process, leveraging custom output generators and automating event-triggered action sequences.
RTL Netlist generation, in addition to makefile scripts for an extensive range of EDA tools

Magillem™️ Registers

Magillem Registers

Benefits

Features

Easy adoption: No learning curve thanks to intuitive yet powerful and extensible register editor GUI. Seamless integration in existing flows thanks to customizable importer/exporter/register property definitions.
Boosted productivity: Produce a correct by-construction IP-XACT description, without requiring IP-XACT expertise. Reduce tedious and error-prone tasks by the automated generation of multiple and customizable output formats.
Consistency: Count on a single source of truth, ensuring synchronization between HW, SW, and documentation databases.

Import of register/bitfields description from CSV, Excel, or CMSIS formats, integrated Design Rule Checks for syntax and semantic errors detection, with on-the-fly markers and contextual resolution help.
Advanced Parameterization including configurable and conditional properties, custom-specific access types, register modes, types, and hierarchical properties.
Merge/Flatten of IP memory Map definition enables easy update, manipulation, and creation that enables incremental design flow and collaborative work coherency.
Generation of C HAL, documentation, System RDL, RTL register bank, and UVM register model synchronized with RTL, flexible generator customization performed through native Object-Oriented API, in a user-friendly template environment editor.

CSRCompiler™️

CSRCompiler

Benefits

Features

Enhanced Flexibility: Collaboratively manage your design from a single source specification, turning address map sharing into a smooth, integrated process to give the entire design team a complete, correct, up to date register design ecosystem.
Design Efficiency: Detect both design function and semantic problems, preventing design mistakes during address map deployment. Ability to easily identify changes and seamlessly ripple through subsequent steps.
Improved Performance: Performance to provide multiple design iterations per day, even for multi-million register designs.

Accept IP-XACT, SystemRDL, spreadsheets and internal formats to generate both industry standard and customized outputs (synthesizable RTL, firmware headers, verification class instances, and documentation outputs)
A built-in ability to validate intellectual property from third-party or internal legacy data, ensuring data is clean, verified, and ready for use.
A true cross-compiler engine producing all required views and formats for register design and the development of the hardware/software interface.
Fully customize outputs no matter the application, with no additional scripting or manual intervention needed.

Harmony Trace™️

Benefits

Features

Higher quality + more predictable schedules: Increases system quality and accelerates functional safety assessments
End-to-end traceability: Across existing systems - requirements, specs, EDA, SW, docs & support
Built to scale: Enterprise-level server-based application with a web-based UI

Can help automatically link data between systems with its unique semiconductor industry-specific semantic computing technology
Continue to use best-in-class solutions and technologies like EDA tools, IBM DOORS, Jama, Jira, DITA, and IP-XACT

Accelerate SoC Integration

Supply Chain Management (SCM)

Streamlined product development starts with a managed supply chain to serve multiple product development streams. Our platform imports, manages and supports review of IP and subsystem releases as they become available. All packaged under the IP-XACT industry standard.

SoC Assembly and Configuration

SoC integrators can draw on this supply chain to drive design around IP instances, connections and NoC interconnects. At any time, the development team can generate work-in-process and final design netlists automatically to drive functionality testing, KPI analysis and signoff.

Automated Documentation Generation

Integrators can, at any time, generate updated software documentation on parametrized functions (clock options and software interfaces, for example). These can be used to update internal specifications and hardware technical reference manuals (TRMs). This data is automatically derived and synchronized with the design and is generated in industry-standard formats for easy insertion in larger manuals.

Asia

Arteris Nanjing
Room 2708, Yunfeng Mansion
No. 8 Zhongshan North Road
Nanjing, China, 210038
安通思半导体技术（南京）有限公司
南京市鼓楼区中山北路8号云峰大厦2708室
邮编 210008
+86 25 58355692

Arteris Seoul
U-Space 2B, #1001,
670, Daewangpangyo-ro Bundang-gu,
Seongnam-si, Gyeonggi-do,
Seoul 13494 Korea
+82 (10) 4704 9526

Arteris Tokyo
#402, 2-10-15 Shibuya, Shibuya-ku
Tokyo, Japan 150-0002
+81 3 4405 0399

Support

Need help? Visit the helpdesk
Semiconductor IP: help@arteris.com
SoC Integration: mds_service_desk@arteris.com