Arteris Articles

Semiconductor Engineering: Racing To The Edge

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments in the latest Semiconductor Engineering article.

Racing To The Edge

April 9th, 2019 - By Susan Rambo and Ed Sperling

The race is on to win a piece of the edge despite the fact that there is no consistent definition of where the edge begins and ends or how the various pieces will be integrated or ultimately tested.

Safety lives at the edge
“The edge includes a lot of the stuff where people are most concerned about things that can kill you, like cars and robots and medical devices,” said Kurt Shuler, vice president of Arteris IP. “These things can kill you two ways. One is a cosmic ray and the traditional functional safety use case, where it flips a bit and then it goes awry. The other way is everything works as intended, however what it does and what it decides to do from its neural net application is the wrong thing. There’s not a cosmic ray. There’s not a hardware safety problem. The safety of the intended function is bad. (There is a new specification out for that, ISO/PAS 21448:2019 Road Vehicles — Safety of the Intended Functionality.)”

For more information on AI, please click on the Arteris FlexNoC AI Package webpage: http://www.arteris.com/flexnoc-ai-package.

Topics: SoC ARM automotive semiconductor engineering safety noc interconnect edge ISO/PAS Intended functionality

Semiconductor Engineering: Big Shift In Multi-Core Design

 Arteris IP's Kurt Shuler, Vice President of Marketing, adds commentary in this article in Semiconductor Engineering.

Big Shift In Multi-Core Design

April 3rd, 2019 - By Ann Steffora Mutschler

System-wide concerns in AI and automotive are forcing hardware and software teams to work together, but gaps still remain.

Minding the gap
There are indications that mindset is beginning to change, particularly in markets such as automotive where systemic complexity extends well beyond a single chip or even a single vehicle.

“In the past, if you were a software engineer, the thinking was, ‘I have this chip available. Here’s what I can produce with my software,'” said Kurt Shuler, vice president of marketing at Arteris IP. “Nowadays, especially in the ADAS side of things that have an AI component or some kind of programmable object detection for the ADAS functionality, or an AI chip—whether it’s for the data center, edge, inference or training—the thinking has shifted more to system-design decisions. If this is designed with this given set of software algorithms, it is clear what needs to happen at a system level from the hardware and software point of view. At what level of detail should I optimize this hardware for the particular software I expect to run? This means the hardware and the software are now much more tightly integrated in those use cases than they probably have ever been unless it’s a very detailed embedded application. So now, in the early stages of design for these types of chips, whether it’s the autonomous driving chips or the AI chips, the software architect is in there, too.”

This is a definite sign of progress. “Before, they didn’t care,” Shuler said. “The layer/API between hardware and software is becoming less generic and more specific for those kinds of use cases, solving those kinds of problems. What that means, though, is there are software guys who went to Stanford and trained on Java script and have no idea what a register is. Then there are hardware guys who have no idea what a hypervisor or object-oriented programming is.”

For more information on AI, please click on the Arteris FlexNoC AI Package webpage: http://www.arteris.com/flexnoc-ai-package.

Topics: SoC software automotive ADAS autonomous driving semiconductor engineering AI hardware noc interconnect

Semiconductor Engineering: AI: Where's The Money?

 Arteris IP's Kurt Shuler, Vice President of Marketing, authored this article in Semiconductor Engineering about Artificial Intelligence (AI), and asks what is hype and what is reality?

AI: Where's The Money?

March 7th, 2019 - By Kurt Shuler

What the market for AI hardware might look like in 2025.

A one-time technology outcast, Artificial Intelligence (AI) has come a long way. Now there's groundswell of interest and investment in products and technologies to deliver his performance visual recognition, matching or besting human skills. We're overwhelmed by possibilities, but what is often less clear is where the money is really going. What is aspiration, what is hype and what is reality?

There are multiple ways to slice this question, such as dividing by applications or implementation choices. At Arteris IP, we have a unique view because our interconnect technology is used in many custom AI designs which, as we’ll see, are likely to dominate the space. Combining this view with recent McKinsey analyses provides some interesting and, in some cases, surprising insights.

Bottom line: AI is big, but there is no such thing as a “standard AI chip.” Optimal chip architectures differ according to the types of functions that must be executed, where they must be performed, and within what amount of time and power budget.

For more information on AI, please click on the Arteris FlexNoC AI Package webpage: http://www.arteris.com/flexnoc-ai-package.

Topics: SoC functional safety automotive semiconductor engineering AI noc interconnect chip architectures datacenters

Semiconductor Engineering: How To Build An Automotive Chip

 Arteris IP's Kurt Shuler, Vice President of Marketing, comments about the claims of technical safety requirements in this Semiconductor Engineering article;

How To Build An Automotive Chip

March 7th, 2019 - By Ann Steffora Mutschler

Changing standards, stringent requirements and a mix of expertise make this a tough marketing to crack.

IP issues
“One of the things that all of these guys deal with is having evidence that the specifications are being followed, both from a process standpoint of how the IP is designed,” said Kurt Shuler, vice president of marketing at Arteris IP. “And then, does the IP meet the technical safety requirements that are being claimed?”

This requires the IP customer to look closely at their different IP providers. “If I’m licensing some IP, I want to understand in pre-sales what do you have, how did you build it,” said Shuler. “What evidence and work products do you have to prove any claims that you make? Things may go quiet for a while until the design team gets closer to the end of the chip design project and starts doing the work where they have to calculate the diagnostic coverage and FMEDA, maybe some fault injection to validate, some of the assumptions they make in the FMEDA, among other activities.”

“If our customer or prospect has somebody who doesn’t understand functional safety or the specification, and is just going blindly through a checklist, it slows things down,” Shuler said. “So the right subject matter experts must be there.”

For more information about ISO 26262:2018 Part 11, please download this presentation "Fundamentals of ISO 26262 Part 11 for Semiconductors".

Topics: SoC functional safety ISO 26262 automotive semiconductor engineering AI RTL noc interconnect ML/AI