Frequent DRAM accesses waste clock cycles and cause performance to drop. CodaCache™ solves these problems by keeping data closer to the access point. You can drop in a CodaCache in your design anywhere there is a need for frequent data accesses. Also, CodaCache can be seamlessly integrated using standard AXI interfaces. It is a truly a standalone product!
Design teams and architects can easily configure CodaCache based on area, timing and other requirements. CodaCache provides the most flexibility of any commercial on-chip last level cache IP. From setting associativity up to 16 ways, to configuring cache sizes and multiple slave ports, you can pick and choose options that will benefit your design to reach its full potential.
Designers can configure portions of a CodaCache instance as a scratchpad RAM. This allows designers to assign a temporary storage where they can keep weights, hash tables, counters or real-time applicable data.
CodaCache also provides options for way partitioning. With way partitioning, each way can be reserved so that only a specific ID or group of IDs can be allocated to that way. These mechanisms help avert resource starvation by greedy threads.
The Arteris IP CodaCache reduces memory bottlenecks and saves power by allowing system-on-chip to employ a highly configurable last-level cache rather than solely communicating with off-chip memory. Designers will be attracted to the variety of use cases that CodaCache IP supports, including dedicated, shared, and distributed partitioning, as well as its use as on-chip scratchpad storage.
Mike Demler, Senior Analyst, The Linley Group & Microprocessor Report
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