• AI chip brain
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  Download FlexNoC AI Package Datasheet

  Download AI & Neural Net Presentation

The optional Arteris® FlexNoC® AI Package automatically generates mesh, ring and torus interconnect topologies. Unlike black box compiler approaches, SoC architects can edit generated topologies and also optimize each individual network router, if desired.

Create highly scalable Ring, Mesh and Torus topologies

Efficiently span long distances across huge chips

Increase on-chip and off-chip bandwidth

Unique capabilities:

  • Highly efficient Multicast / Broadcast writes
  • VC-Link™ Virtual Channels
  • Source Synchronous Communications
  • Automatically generate ring, mesh, and torus networks
  • HBM2 and multichannel memory support
  • Meet ISO 26262 ASIL D requirements with optional Resilience Package
  Download FlexNoC AI Package Datasheet

What industry leaders say about Arteris IP enabling AI and ML chipsets:

After a rigorous evaluation of nearly all commercial solutions, we determined that Arteris FlexNoC interconnect IP was the only NoC technology that would meet all our requirements.

Dr, Daofu Liu, Vice PresidentCambricon

Arteris FlexNoC interconnect IP is the only interconnect that would allow our AI chips to achieve their high bandwidth requirements while also meeting our QoS requirements. Using Arteris NoC technology allows our architecture to take maximum advantage of state-of-the-art HBM2 memories to avoid system-level data starvation, which is major problem with less efficient AI training chips.

Enflame logo
Arthur Zhang, COO, Enflame

Numerous startups are attempting to develop SoCs for neural-network training and inference, but to be successful, they must have the interconnect IP and tools required to integrate such complex, massively parallel processors while meeting the requirements for high-bandwidth on-chip and off-chip communications. Arteris IP has the experience and interconnect IP to help these companies succeed, and FlexNoC 4 with the AI Package provides the features required for AI chips in an easy-to use and highly configurable form.

Mike Demler, Senior Analyst & Senior Editor, The Linley Group & Microprocessor Report