What is cache coherent interconnect?
Cache coherence ensures that all processing elements (PEs) within a system-on-chip (SoC) maintain a consistent view of shared memory. When one PE updates a shared memory location, all other PEs with cached copies are notified so their local caches remain synchronized.
Arteris Ncore Interconnect IP is a cache-coherent network-on-chip (NoC) fabric that connects multiple SoC components using industry-standard coherence protocols. It maintains data consistency between CPUs, GPUs, accelerators, and heterogeneous processing clusters. Ncore supports Arm AMBA coherent protocols including cache Coherent Hub Interface (CHI) and AXI Coherency Extensions (ACE).
Ncore enables seamless interaction across coherent and non-coherent domains, reducing latency, improving performance, and helping to ensure data integrity in complex multi-processor systems.
Cache-coherent vs. non-coherent interconnects
Cache-coherent interconnect
Data coherence: Ensures shared memory remains consistent and up to date across all PEs.
Hardware synchronization: Uses protocols like CHI, ACE, and ACE-Lite instead of software-managed coherency.
Scalability: Implements directory-based snoop filters that track cache contents efficiently across many agents.
Lower latency: Hardware-managed coherency reduces cache maintenance overhead.
Reduced software complexity: Eliminates manual coherency management, simplifying verification and development.
Non-coherent interconnect
No automatic data consistency: Caches operate independently without invalidation or update mechanisms.
More explicit control: Developers manage synchronization manually, which can improve performance for certain workloads.
Independent scaling: PEs operate without shared-memory overhead, reducing resource contention.
Lower inherent latency: No coherence protocol overhead benefits real-time or ultra-low-latency tasks.
Simpler hardware: Non-coherent designs use fewer structures, reducing power, performance and area (PPA).
Choosing the right model
Some subsystems require full cache coherence, while others prioritize low latency, deterministic behavior, or simpler hardware. Many modern SoCs use hybrid topologies combining coherent and non-coherent domains.
Benefits of cache-coherent NoCs
Advantages of cache-coherent NoCs
- Automatically maintains cache consistency between PEs.
- Provides IO coherence interfaces for non-coherent agents.
Simplifies software and firmware by offloading coherency to hardware.
Advantages of non-coherent NoCs
- Enables fine-grained synchronization control.
- Ideal for real-time and ultra-low-latency workloads.
- Uses simpler hardware structures with betterPPA.
Why cache-coherent interconnect is important
Data consistency
PEs rely on caches for fast data access; coherence ensures every agent sees the most recent data state.
Performance optimization
Hardware-managed coherence reduces the need to access main memory, lowering latency and improving throughput.
Simplified software development
Developers can implement multithreaded workloads without manually managing shared caches.
Lower latency
Cache-to-cache transfers are significantly faster than DRAM access, improving system responsiveness.
Scalability
As SoCs integrate more PEs, hardware-managed coherence becomes essential for correctness and performance.
Compatibility
Most operating systems and software assume coherence; hardware support ensures ecosystem compatibility.
Reliability
Avoids data corruption, stale data and race conditions that otherwise lead to instability.
How cache coherent interconnect works
Cache state tracking
Each cache line tracks a state such as Modified, Exclusive, Owned, Shared or Invalid.
Cache-to-cache communication
When one PE writes to shared data, other caches with copies are notified or updated.
Directory-based protocols
Arteris Ncore uses centralized or distributed directory structures that track where each cache line resides, avoiding unnecessary broadcasts.
Snooping
Caches monitor memory access traffic and update or invalidate lines as needed.
Coherence enforcement
Coherence rules ensure correct ordering, visibility, and atomicity across all PEs.
Write propagation and invalidation
Writes either update other caches or invalidate stale copies to maintain correctness.
Atomic operations
Read-modify-write sequences are coordinated across multiple caches to ensure correctness.
Cache coherent interconnect with Arteris Ncore
Heterogeneous cache coherency
Ncore supports heterogeneous coherency models, accommodating PEs with different behaviors and coherence attributes.
Multiple snoop filters
Snoop filters can be grouped per PE or shared across clusters to improve area efficiency.
Scalability
Ncore scales interconnect capacity, number of agents, ports and bandwidth without over-designing unused paths.
High-performance links to non-coherent PEs
Proxy caches enable non-coherent PEs to operate IO-coherently within coherent subsystems.
Hybrid approaches allow legacy IP such as DSPs, codecs, and I/O controllers to communicate efficiently.
Lower power consumption
Multiple clock domains allow coherent agent interfaces to operate at optimal voltage and frequency.
Easier chip layout
Compact, flexible network interfaces can be placed near their associated IP blocks to minimize routing congestion.
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