EDN: SoC design: When a network-on-chip meets cache coherency

by Andy Nightingale, On Jan 24, 2024

Many people have heard the term cache coherency without fully understanding the considerations in the context of system-on-chip (SoC) devices, especially those using a network-on-chip (NoC). To understand the issues at hand, it’s first necessary to understand the role of cache in the memory hierarchy.

Cache in the memory hierarchy

Inside a CPU are a relatively small number of registers with extremely high speed. These registers can be accessed by the CPU in a single clock cycle. However, their storage capacity is minimal. In contrast, accessing the main memory for reading or writing data takes up many clock cycles. This often results in the CPU being idle most of the time.

In 1965, a British computer scientist, Maurice Wilkes, introduced the concepts of cache memory and memory caching. This involved having a small amount of fast memory called a cache adjoining the CPU. The word “cache” itself comes from the French word “cacher,” meaning “to hide” or “to conceal,” the idea being that the cache hides the main memory from the CPU.

This process operates based on two key points. First, when a program running on the CPU does something involving one location in the main memory, it typically performs operations on several nearby locations. Consequently, when the CPU requests a single piece of data from the main memory, the system brings in data from nearby locations.

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