Overview
Distributed NoC topology provides a scalable and physically efficient alternative to traditional hierarchical bus or crossbar interconnects. Instead of relying on a centralized switching structure, Arteris network-on-chip (NoC) technology distributes routing, buffering, and protocol-conversion elements throughout the chip. This reduces routing congestion, simplifies timing closure, and enables more predictable physical convergence.
Distributed architecture for easier routing
Arteris NoC architectures use fewer global wires and gates than traditional interconnects. Switches, FIFOs, and other routing elements are implemented as compact, localized units that can be automatically placed in small regions across the die. This modular distribution minimizes routing bottlenecks and aligns the interconnect naturally with the physical constraints of the floorplan.
Optimized placement of network interface units
Network interface units (NIUs) perform packetization, serialization, and protocol conversion. Because NIUs are physically located next to their corresponding IP blocks, they reduce long‑distance wiring, improve timing predictability, and eliminate back-end placement conflicts. With most protocol complexity isolated in NIUs, the transport fabric remains lightweight and easy to close.
Contrast with traditional bus and crossbar architectures
Traditional bus and crossbar architectures rely on monolithic switching structures placed between IP blocks. These central structures create severe placement pressure and routing congestion as numerous wide buses must be threaded through constrained spaces. As IP counts grow, these issues become unmanageable and limit scalability.
Arteris distributed NoC topology avoids these challenges by eliminating centralized fabrics and allowing routing resources to scale modularly with the layout.
In summary
Arteris distributed NoC topology delivers a scalable, congestion‑free, and physically optimized interconnect architecture. By distributing routing elements and placing NIUs close to IP blocks, the NoC improves routing efficiency, simplifies timing closure, and outperforms traditional bus and crossbar approaches in modern system-on-chip (SoC) designs.
