Automates Topology Creation for
Advanced AI, DNN and ML Systems,
Enhancing Scalability and Flexibility

Generating mesh, ring, and torus topologies for AI, DNN, and ML designs poses challenges in scalability, latency, fault tolerance, and data communication efficiency.

The XL Option automatically generates these interconnect topologies. Unlike black box compiler approaches, SoC architects can edit generated topologies and optimize each individual network router.

Additionally, it also expands the number of NoC initiators and targets, allowing for the integration of a larger number of IP blocks and components within the system ensuring seamless integration of diverse functionalities.

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FlexNoC XL Option

Enables designers to handle higher data volumes and optimize system performance

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Flexible Topologies

Create highly scalable Ring, Mesh and Torus topologies.

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Small to Large SoCs

Efficiently span long distances across huge chips.

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Higher Bandwidth

Increase on-chip and off-chip bandwidth.

XL Option
Key Features

  • Mesh-based interconnect generation
  • Expanded number of NoC initiators and targets
  • Broadcast links, virtual channels and and source-synchronous communications.
  • Support of data widths up to 1024 bits
  • High Bandwidth Memory (HBM) support such as HBM2/HBM2E/HBM3
  • Multichannel memory support
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XL Option Product Benefits

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Advanced Scalability
and Flexibility

Via mesh-based interconnect generation.

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Seamless Integration of IP Blocks and Components

Leads to optimized system functionality.

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Enhanced Communication Efficiency

Improves overall system performance and ensures smooth operation even in highly interconnected designs.

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Increased Data Widths for Higher Data Volumes

Improves system performance and accelerating data-intensive computations.

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High Bandwidth Memory
(e.g. HBM2/HBM2E/HBM3)

Enhances the system's ability to handle large amounts of data, leading to improved performance.

Read more about why we are unique on our NoC Technology page.

Arteris FlexNoC interconnect IP is the only interconnect that would allow our AI chips to achieve their high bandwidth requirements while also meeting our QoS requirements. Using Arteris NoC technology allows our architecture
to take maximum advantage of state-of-the-art HBM2 memories to avoid system-level data starvation,
which is major problem with less efficient AI training chips.

Arthur Zhang

COO of Enflame

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