Arteris FlexNoC product description

Arteris FlexNoC Version 3 Interconnect IP

Arteris® FlexNoC® Version 3 has been released! Read the press announcement here.

The development goals for FlexNoC v3 were to increase SoC designer productivity while providing a foundational platform for future IP technology development.

New FlexNoC Version 3 features include:

  • Switch-based topology editor – It is now easier to create, characterize and modify large designs while keeping access to the entire SoC topology available within a single view.
  • Topic- and activity-based user interface – Years of customer feedback and human factors research have resulted in a streamlined interface that makes it easier for SoC architects and designers to perform complex and repetitive tasks.
  • NoC composition enhancements – Users can more easily break large interconnect designs into smaller modules for implementation by different sub-teams, and can quickly combine separate designs or modules into a single interconnect instance for integration.

Existing customers are encouraged to upgrade to FlexNoC v3. Please contact your sales manager to learn more!

What is FlexNoC?

Arteris® FlexNoC® provides on-chip connectivity for SoC IP blocks implementing any combination of AMBA® AXI™, AHB™, AHB-Lite, APB™, OCP and PIF protocols.

Arteris FlexNoC is for SoC interconnects with low latency and high throughput requirements. FlexNoC provides support for the features needed by today’s SoCs, such as clock domain conversion, QoS, debug visibility and security.

FlexNoC includes FlexExplorer for quick interconnect simulation and iteration to reduce development time. FlexExplorer's OSCI SystemC TLM 2.0 models can be easily exported for us in industry-leading system-level simulation tools.

Advanced features include:

  • FlexMem Memory Scheduler
  • On-chip Debug, Tracing, and Statistics Collection
  • Multiple Power Domain Management for Dynamic Voltage and Frequency Scaling (DVFS)

Why FlexNoC?

Eliminate Routing Congestion

Arteris NoC IP reduces routing congestion by taking advantage of variable link widths and packetization to selectively reduce the number of wires required to meet system throughput and latency constraints.

FlexNoC Features
Arteris FlexNoC Features
FlexArtist (Main GUI)
Arteris FlexNoC Features
FlexExplorer - for quick simulation and iteration
Arteris FlexNoC Features
FlexVerifier ATE - Automated testing and verification environment
Arteris FlexNoC Features
FlexVerifier VMM verification environment
Arteris FlexNoC Features
Support for unlimited number of initiators and targets
Arteris FlexNoC Features
AMBA AHB/APB/AXI protocol support
Arteris FlexNoC Features
Full OCP and OCP lite protocol support
Arteris FlexNoC Features
Tensilica PIF protocol support
Arteris FlexNoC Features
Support for 8 to 256 bit data path widths
Arteris FlexNoC Features
Advanced QoS- Bandwidth Regulation, Rate Limitation, software programmable traffic priorities
Arteris FlexNoC Features
Power disconnect at socket boundary
Arteris FlexNoC Features
Error Logging support
Arteris FlexNoC Features
Security - Basic Firewall and Fixed Security Support
Arteris FlexNoC Features
Advanced Security - User Defined Firewalls and Security Policies
Arteris FlexNoC Features
FlexMem Memory Scheduler
Arteris FlexNoC Features
On-chip Debug, Tracing, and Statistics Collection
Arteris FlexNoC Features
Multiple Power Domain Management for Dynamic Voltage and Frequency Scaling (DVFS)

Whether you are using AMBA AXI3, AXI4, AHB, APB, OCP, PIF or a proprietary protocol, Arteris FlexNoC IP reduces the number of wires by nearly one half, resulting in fewer gates and a more compact chip floor plan.

Ease Timing Closure

Timing closure is simplified by allowing the designer to easily and precisely place pipelines/register slices at specific locations in the interconnect to resolve timing issues. This means timing issues found late in the design cycle can be resolved without having to modify the SoC netlist or re-architect the interconnect.

Springer Verlag Journal Design Automation for Embedded Systems peer reviewed article by Arteris

Speed Time to Market

Arteris FlexNoC makes it easy to develop, verify and iterate interconnect configurations by providing intuitive GUI and scripting interfaces. Out of the box support for all the major IP transaction protocols makes it easy to replace IP to create SoC derivatives or make IP changes late in the design cycle.

Integrated FlexExplorer simulation automatically generates OSCI SystemC TLM 2.0 interconnect models at three levels of abstraction for quick turn-around performance evaluation of interconnect configurations.

Reduce Power Consumption with Clock Gating and Frequency / Voltage Domains (DVFS)

FlexNoC includes support to turn of the clocks of IPs that are not being used. Addition options are available for more advanced clock gating, power domain, and dynamic frequency and voltage scaling (DVFS) capabilities.

Advanced Quality of Service

FlexNoC includes Quality of Service features out of the box that propagates master / initiator QoS information (such as AXI QoS information) through the interconnect and to the target.

This end-to-end QoS solution is for on-chip data flows that must meet concurrent bandwidth and latency requirements from the initiator, through the interconnect, and then through the memory controller.

FlexMem Memory Scheduler

In addition, Arteris offers the optional FlexMem Memory Scheduler to ensure QoS through to the memory controller while reducing on-die routing congestion and timing issues near the memory controller.

Automated Verification for Lowest Risk

In addition to RTL and the three levels of SystemC TLM 2.0 models provided in FlexExplorer, FlexNoC includes the FlexVerifier Automated Test Environment (ATE) and the FlexVerifier VMM verification environment.

routing congestion solved by network on chip interconnect for SoC