Close Timing Sooner with
FlexNoC Physical™

Arteris® FlexNoC® Physical builds upon the already layout-friendly FlexNoC IP to shorten the time required for timing closure, physical synthesis and place and route (SP&R).

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Arteris FlexNoC Physical interconnect IP builds upon the already layout-friendly FlexNoC IP to shorten the time required for timing closure, physical synthesis and place and route (SP&R).

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FlexNoC Physical interconnect IP enhances layout quality-of-results (QoR) and productivity by importing user-defined and production (LEF/DEF) floorplans, automatically configuring pipelines to meet timing closure, and separating the FlexNoC interconnect IP instances at a physical level so they can be routed separately from the rest of the SoC.

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  • Saves time: Reduces or eliminates excessive P&R iterations – To resolve timing closure errors on long paths, SoC designers often have to iterate over multiple P&R runs, which can take weeks. Optimizing the NoC interconnect IP early, prior to full SoC P&R, reduces the likelihood of timing closure issues during layout.

  • Eliminates trial-and-error timing closure with automated pipeline configuration – By analyzing the interconnect IP in the front-end design phase and automatically configuring pipeline stages as appropriate, the front-end teams hand over to the back-end team a netlist that will close timing by design.

  • Optimizes Quality-of-Results (QoR) – SoC teams often over-design their chips in the front-end stage to avoid timing problems in the back-end. FlexNoC Physical IP intelligently estimates and predicts in the front-end phase where timing issues will occur in the back-end, allowing design teams to implement the minimum number of pipeline stages to achieve desired frequencies, while also minimizing latencies and power consumption.

  • Separates the FlexNoC interconnect physical IP from the rest of the SoC – FlexNoC Physical can separate the interconnect IP at the physical level the same way that it allows such isolation at the architectural level. Users can now generate interconnect floorplan outlines and treat the interconnect as a separate IP to be independently placed and routed by itself. This separation simplifies the job of the layout team.

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FlexNoC Physical enables not only automated timing closure, but also earlier visualization of the floorplan impacts of the SoC architecture.

Understanding early in the design process where routing congestion and timing closure issues might occur allows the front-end team to make changes to the SoC design, before it reaches the back-end place and route team. 

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After a complete evaluation of available interconnect fabric IP products, Arteris FlexNoC was the clear choice. FlexNoC is the only SoC fabric that allows us to meet tight timing margins and achieve design frequency requirements. We are pleased with the increased productivity our design team has experienced using FlexNoC.

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Ty Garibay, Vice President, Silicon Systems Development, Altera