PIANO Timing Closure Package

The BENEFITS of PIANO 2.0 include:

Slashes the time needed to close timing compared to manual pipeline insertion methodologies, which reduces overall schedule risk. With a well-defined methodology, interconnect timing can be closed in as little as 24 hours.
Shrinks interconnect area by 10-15% compared to manual pipeline insertion methodologies, which over-provision pipeline stages
Decreases interconnect power consumption due to less pipeline logic and use of fewer low voltage threshold (LVT) cells
Provides seeding of pipeline stage locations which allows place and route tools a better starting point, eliminating costly place and route cycles

New CAPABILITIES in PIANO 2.0:

Automated interconnect timing closure for both cache coherent and non-coherent interconnect subsystems
Generation of a meta-floorplan from an IP list to provide timing closure guidance during the SoC architectural development phase
Input and output of production floorplans in LEF/DEF and TCL formats
Automatic pipeline insertion with advanced features:
Edit timing closure parameters to optimize individual timing paths
Automatically account for crossing between multiple frequency and voltage domains
Automatically generate timing closure analysis reports
Integrated with Synopsys’ Design Compiler Graphical and IC Compiler II and Cadence’s Genus and Innovus physical synthesis tool chains.

PIANO 2.0 automated closure technology lowers the risks in SoC development schedules that traditionally result from timing closure issues. By applying PIANO 2.0 together with generated placement guides, Renesas was able to close the complex SoC development sooner than we expected. Renesas has been an early user of Arteris’ closure technology, and we plan to continue to use Arteris’ enhanced closure capabilities for our future SoC developments.

Horst Rieger, Manager, Design Services, European Technology Center, Renesas Electronics Europe