EDN Article: How physically aware interconnect IP bolsters SoC design
byOn Mar 07, 2023
Majeed Ahmad, Editor-in-Chief of EDN, authored this article about Arteris’ FlexNoC 5.
February 23rd, 2023 – By Majeed Ahmad
The network-on-chip (NoC) technology, which connects IP blocks in highly complex system-on-chip (SoC) designs, has ascended to the next logical level by becoming physically aware. According to Andy Nightingale, VP of product marketing at Arteris, that accelerates the exploration of the needed space to achieve an optimal NoC topology at the front-end and speeds up timing closure at the back-end. Arteris has unveiled its next-generation interconnect IP, FlexNoC 5, which it calls the first physically aware NoC technology. It’s aimed to allow SoC architecture teams, logic designers, and integrators to incorporate physical constraint management and achieve faster physical convergence over manual refinements with fewer iterations from the layout team.