Semiconductor Engineering: Power Optimization Strategies Widen

by Madelyn Miller, On Jun 14, 2018

May 10th, 2018 – By Brian Bailey

Different markets are heading in different directions, raising questions about whether the chip industry can effectively respond to all those demands.

{{cta(‘e989304e-741e-4693-a19f-18865d3293db’)}}

Many components of a car are modular in this fashion. “Idle power is not a problem for modular pieces because either the device is active or off,” says Benoit de Lescure, director of application engineering for Arteris IP. “An example would be complex SoC to do autopilot of the car. When it is active, you can be sure that all of the silicon on the SoC is going to be active. An image will come at a particular rate, there will be no idle periods where power can be saved. Developers will attempt to work at the algorithmic level to minimize the transfer of data between the external memory, or by adding a cache you reduce the amount of time you spend going to an external DRAM. This saves on power.”

To read the entire article, please click here:
https://semiengineering.com/power-optimization-strategies-widen

Subscribe to Arteris News