Semiconductor Engineering: 7nm Design Challenges Video
, Jul 23, 2018
Tech Talk Video: 7nm Design Challenges
July 9th, 2018 – By Ed Sperling
Ed Sperling interviews Ty Garibay, CTO at Arteris IP headquarters about the challenges of moving to 7nm, who’s likely to head there, how long it will take to develop chips at that node, and why it will be so expensive. This also raises questions about whether chips will begin to disaggregate at 7nm and 5nm.
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To see the video, please click here:
https://semiengineering.com/7nm-design-challenges
