Semiconductor Engineering: IP and Power

by Kurt Shuler, On Mar 09, 2018

March 8th, 2018 – By Brian Bailey

How do system designers ensure that the complete system has an optimal power profile, and what can they do to tune each of the IP blocks to ensure that overall power is minimized?
There is a fine balance between what the IP industry can provide and the needs of the system designer. But there is almost universal agreement that power optimization needs to be pervasive throughout the development flow.
Power can be optimized in several ways. “Power optimization techniques fall into three categories,” says Alexis Boutillier, functional safety and corporate application manager for ArterisIP. “One is linked to the actual application running at the SoC level, which saves the most power but requires additional logic and interfaces to enter and leave a power state. Then we have an intermediate level, where by correctly architecting your design you can automatically stop the clock for a complete element of the IP. Lastly, we have a low-level optimization done by a synthesis tool, which relies on good design of IP elements.”
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