I recently talked with Frank Schirrmeister (Solutions & Business Development, Arteris) on the state of progress to the open chiplet ideal. You know – where a multi-die system in package can be assembled with UCIe (or other) connections seamlessly connecting data flows between dies. If artificial general intelligence and industrial-scale quantum computing are right around the corner, surely any remaining issues in open chiplet design should be a snap to resolve? According to Frank, the answer is yes and no. For a couple of privileged groups, anything is possible and is being put into practice today. For larger open markets, not so much, at least not in the near term.

Multi-die systems and proprietary solutions

Multi-die systems address the never-ending demand to build bigger and more complex systems (for LLM processing as one example) when constrained by a number of semiconductor limitations: you can only fit so much logic on one die; some functions like analog and DRAM work best in processes which are not optimal for logic; and even if you could somehow fit more onto a single die, yield would plummet and costs would soar.

Within the last year or so, Intel, AMD, and Nvidia all released processor products based on chiplet architectures. What is unique to these products in this context is that these companies each built all their own chiplets, together with the infrastructure and connectivity assembling them into a full multi-die system. They have no dependency on external chiplet providers or external chiplet-to-chiplet communication IP providers. By controlling everything internally, and guiding their suppliers accordingly, they can tune and validate the systems they built in-house against their own extensive suites of tests. Some other very large vertically integrated companies may also fall in this class. I am told that Meta may now be one of these, and I would be surprised if Apple was not also handling all their own multi-die design.

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