Having precise control over the configuration of coherent agent ports, memory interfaces, and snoop filters helps us make more power- and area-efficient SoCs. The distributed hardware architecture allows for a more efficient physical design by easing back-end placement and timing closure.
Benny Chang, Vice President of R&D, Automotive MCU and Processors Business Line, NXP Semiconductors
The exploding cost of the latest semiconductor process nodes is forcing design teams to evaluate new architectural approaches for SoC design. The distributed cache coherent architecture that Arteris offers will help system designers better utilize the processing resources in the SoC, making computing throughput more efficient.
Linley Gwennap, Principal Analyst, The Linley Group