An optional add-on for Arteris® FlexNoC® interconnect IP that helps automate interconnect timing closure.
PIANO provides more and better physical and timing information about the interconnect to back-end SP&R tools to help ensure faster timing closure.
With interconnect logic location hinting and automated pipeline optimization
The PIANO Timing Closure Package enhances layout quality-of-results (QoR) and productivity by importing user-defined and production (LEF/DEF) floorplans, automatically configuring pipelines to meet timing closure, and separating the FlexNoC interconnect IP instances at a physical level so they can be routed separately from the rest of the SoC.
Less effort, less time, less money. Better results.
Arteris users solve back-end problems before they happen
PIANO 2.0 automated closure technology lowers the risks in SoC development schedules that traditionally result from timing closure issues. By applying PIANO 2.0 together with generated placement guides, Renesas was able to close the complex SoC development sooner than we expected. Renesas has been an early user of Arteris’ closure technology, and we plan to continue to use Arteris’ enhanced closure capabilities for our future SoC developments.
Horst Rieger, Manager, Design Services, European Technology Center, Renesas Electronics Europe
Arteris PIANO Timing Closure Package accelerates the interconnect timing closure of Arteris FlexNoC interconnect IP.
After a complete evaluation of available interconnect fabric IP products, Arteris FlexNoC was the clear choice. FlexNoC is the only SoC fabric that allows us to meet tight timing margins and achieve design frequency requirements. We are pleased with the increased productivity our design team has experienced using FlexNoC.