Arteris Articles

Arteris IP at Synopsys Users Group Silicon Valley 2019


Arteris IP at SNUG Silicon Valley 2019 

Location: Santa Clara Convention Center, 5001 Great America Parkway, Santa Clara, CA  5309079302d859475117e5e14f041224_SNUGgeneric_ver_O_2
Track: Artificial Intelligence - Wednesday, 20 March, 3:45 pm - 4:30 pm

Arteris IP is presenting this paper, "Using Machine Learning for Characterization of NoC Components"

Abstract: 
Modern NoC (Network-on-Chip) is built of complex functional blocks, such as packet switches and protocol converters.  PPA (performance/power/area) estimates for these components are highly desirable during early design phases – long before NoC gate level netlist is synthesized. At this stage a NoC component is a soft module, described by a set of architectural parameters, like the bit width of ingress and egress ports, number of virtual channels, etc.

The proposed approach attempts to predict the PPA behavior of NoC components based on machine learning non-linear regression algorithms.  The system consists of several layers. At the bottom Synopsys Physical Compiler is used to synthesize a NoC component with one combination of input parameters (features) and capture its characteristics. This result becomes a data point in a training set. When it gets sufficiently large, this set is being used for training fast models predicting PPA for components with parameter values not exercised during the training.  These models can be plugged into a NoC design tool assisting the user with feasibility and what-if analysis.

Speaker: Benny Winefeld - Arteris IP


Registration: https://event.synopsys.com/ereg/newreg.php?eventid=396238

For more information, please download the FlexNoC Interconnect IP datasheet; https://www.arteris.com/flexnoc

Additional resources are available here; https://www.arteris.com/resources

 
Topics: NoC semiconductor noc interconnect SoCs PPA ML Soft IP FlexNoC RTL