Arteris Articles

Arteris IP is Presenting at The Linley Spring Processor Conference April 10 - 11, 2019!


Don't Miss the Arteris IP Presentation on AI SoC Architectures, Thursday, April 11, 2019 

SPC19-320x84_sponsor-bannerLocation: Hyatt Regency, Santa Clara, CA
Session 5: SoC Design: Thursday, April 11
1:15 pm - 2:45 pm

Arteris IP presenting: "Adapting SoC Architectures for Types of Artificial-Intelligence Processing"

Come to the Linley Spring Processor Conference on April 10 - 11, 2019  - and attend the Arteris IP presentation on Thursday, April 11 during Session 5: SoC Design, were we will describe lessons learned on how to use network-on-chip (NoC) technology to efficiently implement SoC architectures targeted for different types of AI processing, including advanced techniques like when to use tiling or cache coherence, whether for edge/battery-operated or datacenter chips. 

April 11 Agenda: https://www.linleygroup.com/events/agenda.php?num=46&day=2

Abstract: "
AI" is often used abstractly to refer to systems (and chips) that implement machine-learning algorithms. But different types of chips are required for different types of AI/ML processing, whether for neural-network training or inference, or for a data center or battery-powered client. This presentation describes how to use network-on-chip (NoC) technology to efficiently implement SoC architectures targeting different types of AI processing, including advanced techniques such as when to use tiling or cache coherence.


Presenter: Matthew Mangan - Arteris IP

Talk with our experts and visit with us during the Networking Reception on Wednesday, April 10 from 4:45 pm - 6:15 pm

For more conference information: https://www.linleygroup.com/events/event.php?num=46

Register Today: https://www.linleygroup.com/events/register.php?num=46

For more information about Arteris IP, download the FlexNoC AI Package datasheet: http://www.arteris.com/download-flexnoc-ai-package-datasheet

 
 

 

Topics: NoC semiconductor ArterisIP artificial intelligence SoCs edge/battery-operated cache coherence datacenter chips