Arteris Articles

SemiWiki: AI, Safety and Low Power, Compounding Complexity

Bernard Murphy talked to Kurt Shuler about the complexities of combining low power, safety and AI constraints in a design. Design challenges have evolved beyond PPA to encompass new constraints but these are still manageable, with the right architecture in this new SemiWiki blog:

AI, Safety and Low Power, Compounding Complexity 

April 28th, 2020 - By Bernard Murphy

The nexus of complexity in SoC design these days has to be in automotive ADAS devices. Arteris IP highlighted this in the Linley Processor Conference recently where they talked about an ADAS chip that Toshiba had built. This has multiple vision and AI accelerators, both DSP and DNN-based. It is clearly aiming for ISO 26262 ASIL D certification since the design separates a safety island from the processing island, pretty much the only way you can get to ASIL D in a heterogenous mix of ASIL-level on-chip subsystems. Equally clear, it’s aiming to run at low power – around 2.7W for the processing island (the bulk of the functionality). It’s all very well to be smart but when you have dozens of smart components scattered around the car, that adds up to a lot of power consumption. The car isn’t going to be very smart if it runs its battery flat.

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To read the entire article, please click here: https://semiwiki.com/automotive/284905-ai-safety-and-low-power-compounding-complexity/ 

Topics: SoC ISO 26262 semiconductor Toshiba ADAS Ncore FlexNoC AI semiwiki ASIL D noc interconnect memory hierarchy