Arteris Articles

Advanced SoC Interconnect IP Enables Greater Flexibility in an Era of Consolidation

I am thoroughly enjoying 2013. That’s because there seems to be a lot more reason for optimism this year than last year.  But before we let go of 2012, it’s important to reflect on the past year and see what it can teach us so we can make better business decisions moving forward.

Topics: semiconductor industry SoC economics IP economics intellectual property semiconductor industry economics NoC software network-on-chip network-on-chip research ASICs ASIC design FPGAs field programmable gate arrays FPGA design cores on-chip interconnect

The Gartner Hype Cycle & Technology Adoption Lifecycle Explained (using NoC Technology)

My purpose in this article is to explain Gartner Research’s Hype Cycle and relate it to the Technology Adoption Lifecycle popularized by Geoffrey Moore’s book, “Crossing the Chasm.”  These two models can be used together to provide a combined picture of market expectations and expected technology adoption rates, but people often get the timeframes and takeaways wrong. So if you’re involved in technology as an engineer, marketer or manager, read on!

Topics: semiconductor industry economics network-on-chip research Gartner

NoC Interconnect Technology Becoming Mainstream

Gartner analyst Jim Tully’s assessment that network on chip (NoC) technology will be “mainstream” in two to five years is an acknowledgement of the technical and commercial success NoC interconnect IP has had in the consumer electronics system on chip (SoC) market over the last couple of years.

Topics: interconnect IP network-on-chip network-on-chip

NoC is not a Noun

As featured in:
Today in the IP and EDA business, I hear “knock” all the time, except people mean “NoC.” It seems everybody wants a NoC, or wants to offer you a NoC. I’m here to tell you that NoC is not a noun.
Topics: NoC network-on-chip network-on-chip Networks-On-Chip