wire routing congestion solved by network on chip interconnects

Routing Congestion

Wire routing congestion is a leading cause of late and underperforming chips designs. Traditional means to deal with routing congestion overlook the root causes and only treat the symptoms in the latter layout and place-and-route backend phases of chip design. In the worst cases, designers must increase die size or the number of metal layers to reduce routing congestion. Arteris network-on-chip interconnect fabric IP allows SoC designers to reduce and remove routing congestion in the architecture phase of design by reducing the number of interconnect wires that will need to be routed. We provide a front end solution to a back end problem.

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routing congestion in an AMBA AXI NIC-301 interconnect
Routing congestion in an AMBA AXI NIC-301 interconnect. Source: Customer design.
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What is Routing Congestion?

Wire routing congestion occurs on a system-on-chip when a lot of wires (or metal lines) are routed in a narrow space. Signal wires that carry data are most subject to congestion because they are routed after the power supply and clock wires and therefore subject to additional constraints. These power supply and clock wires usually occupy the upper-level metal layers where the wires have wider and taller profiles than the mid- and lower-level metal layers. As a result, signal wires are constrained because they must be routed in a manner that accommodates the existing power supply at clock wires.

metal layers increase in size and number with each new process node
Metal layers grow in size and number with each process node advance
Source: Charles J. Alpert and Gustavo E. Tellez, "The Importance of Routing Congestion Analysis" DAC47

To perform wire routing, EDA tools divide a system-on-chip into grid cells or “g-cells”. These cells may also be called “bins” or “global routing tiles”. Each g-cell only accommodates a finite number of routing wires.

a chip is split into cells called g-cells
A chip is divided into squares called "g-cells" or "bins"
 

Routing congestion is usually measured as a number with 1.0 being 100% congested, 0.5 being 50% congested and so on. This number is calculated by taking the area of a g-cell and dividing it by the area required to route all the wires wanting to traverse that cell. Note that this wire area includes the width of the wires as well as the dielectric insulation and lateral spaces around the wire to ensure no crosstalk or impedance issues with neighboring wires.

In systems-on-chip, routing congestion is most likely to occur near heavily used IP sockets, like a DRAM memory controller, and near input/output pads and pins.

What causes Routing Congestion?

As SoC designs become more complex, routing congestion increases. SoC complexity is enabled by the shrinking sizes of transistors, which creates the following effects:

  • More transistors per area allows for a larger and more complex SoC design in the same area as older generation chips. Chip designers take advantage of smaller transistors by packing increasing functionality into each new generation chip, usually by adding blocks of semiconductor intellectual property (IP).
  • A larger SoC enables the opportunity to integrate more IP blocks on one chip. The number of wires required for a system on chip grows proportionally to the square of the number of transistors on the chip. The number of IP blocks can be estimated as varying approximately proportionally with the number of transistors.
  • In addition to requiring more wires, the cross sectional size of wires connecting IP blocks shrinks less than the size of the transistors.

Adding new metal layers is costly

Wires don’t scale as well as the transistors

Wire sizes are not able to shrink at the same rate as transistors. This is because as a wire shrinks, its resistance increases. On average, wire resistance per unit length doubles each process generation, while capacitance stays the same. Assuming transistor scaling of 70% for each process generation change, even though wire length decreases, the delay stays the same. This contrasts with the delays of transistors, which speed up in proportion with the scaling factor with each process generation.
The end result is that the performance benefits of smaller transistors are lost through wire delays.

Need to space wires out more for each new process technology

Also, to handle increasing switching frequencies of each new process technology, wires need to be spaced out more in relation to each other than in previous technologies to reduce capacitance and crosstalk. This means there is no 1:1 scaling even if IP blocks are reused from the old generation to the new generation.

wires do not scale at the same rate as transistors
Metal layers do not scale down proportionally to transistor scaling
Source: Saxena, Prashant, Shelar, Rupesh S., Sapatnekar, Sachin, "Routing Congestion in VLSI Circuits," Springer, 2007.
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The 3 Evils of Routing Congestion >>>

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routing congestion solved by network on chip interconnect for SoC