Arteris Ncore Cache Coherent Interconnect IP Featured in Linley Group Paper

by Kurt Shuler, On Aug 25, 2016

This 9-page paper explains new hardware interconnect IP technology that enables cache coherent communication between different types of compute engines in an SoC. It is written by Senior Analyst Loyd Case of The Linley Group, which also publishes Microprocessor Report and is one of the premier semiconductor analyst groups in our industry.

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