As featured in:
The IP-SoC conference panel, “IPs on FPGA: Strategy and Vision,” was a learning experience for me. Coming from the software and silicon/ASIC/ASSP worlds, I thought I had a pretty comprehensive view of all the various IP licensing models and their technical implementations. But I learned something new that makes me feel positive about the FPGA’s abilities to finally offer a robust market of third party IP.
Before I get into that, let’s step back a bit. If you look at the past, the business models of the FPGA vendors and IP vendors clashed: As Rick Tomihiro (Xilinx), Bob Blake (Altera) and Tim Schnettler (Lattice) made clear on the panel, the goal of the FPGA vendor was to ship silicon. The IP that the customer would need to create a working product was something of an afterthought.
FPGA companies could try to address the issue by providing a “buffet” of partner IP that an FPGA customer could pull from, but it was impossible for FPGA vendors to track what IP was used in each FPGA the customer shipped. There simply aren’t many IP companies willing to accept the economics of this. So even though the customer would love to have a “one-stop shop” and a “menu” of IP options from the FPGA vendor, he was left to select and contract for the IP on his own.
But Rick Tomihiro brought up an interesting question: What if FPGA vendors could be a channel for IP and could track what IP each customer purchased and used? How would this change the business model for FPGA vendors? Could they become that mythical “one-stop shop” for their customers?
My first thought as an IP vendor was, “Sounds intriguing.”
Depending on what numbers you believe, there are about 10x the number of FPGA design starts as ASIC/ASSP design starts. The volume sold per design start is less, but some of these FPGAs go into some really high-value applications, like telecom back-end equipment, mil/aero and others. That means there are value pricing options for IP vendors.
How could this be done? Rick talked on the panel about a company called “Intrinsic ID” that offers a way for an FPGA vendor to sell a certain number of IP instances to a customer, and ensure that no more than the purchased instances could work on any FPGA.
How does it work? I called Tim Smith from Intrinsic ID to learn more. During a one-time “enrollment process”, the Intrinsic ID process creates an “electronic fingerprint” of the physical characteristics of each FPGA sold by the FPGA vendor. This fingerprint is a called a “physically unclonable function” or “PUF” (Note: Wikipedia has a really interesting article on this approach). The FPGA customer then uses an IP-specific smart card to activate each “locked” IP that is downloaded onto the FPGA. The card stores the number of IP instances allowed by contract and decrements this number each time an IP is enabled on an FPGA. This makes it impossible for the IP to be used on anything other than the allowed FPGAs.
Why is this exciting to me?
As a provider of configurable interconnect IP, I want to be able to serve FPGA customers a flow and product that are very similar to what I use for ASIC/ASSP customers. I also want to be able to offer a price for my IP commensurate with the value I add to the customer’s product and his volume. And for those FPGA customers that prefer to get their IP from their FPGA vendor, I want to make it easy for them to purchase from me.
If the FPGA vendors use something like Intrinsic ID, then perhaps we will finally have business model options that make sense for the end customer, the FPGA vendor and the IP vendor.Chart courtesy of Intrinsyc ID