Last week, Arm launched their new “Automotive Enhanced IP Products,” a new suite of automotive technologies to help cut development cycles by up to two years and meet vehicle performance, safety, and AI demands.

This launch is a prime example of how ecosystems work together to accelerate schedules and improve quality and, in this case, safety. The “Arm Ecosystem of Trust” features 66 partners, and Arm emphasized both the software and hardware aspects in respective Blog posts. In “Ecosystem Collaborations Bring Full Stack Software Solutions to Develop Leading-edge Automotive Applications From Day One” Robert Day describes how the full stack software solutions allow automotive partners to innovate using virtual platforms immediately. Focused on the hardware aspects, Tom Conway describes in “Arm’s Broadest Ever Automotive Enhanced IP Portfolio Designed for the Future of Computing in Vehicles” how Arms’ new Automotive Enhanced (AE) processors deliver AI-accelerated computing for automotive markets.

One critical part of Tom’s article is the description of how the ecosystem works:

“Arm has always embraced open standards, as this enables a rich ecosystem of partners to thrive when using the Arm AE IP designs, while also enabling greater portability and software re-use. A great example is Arm’s partnership with Arteris where we have enabled Arteris to validate their own interconnect products (NCore and FlexNoc) using our latest CPU IP. More recently, Arm and Arteris have been validating combinations of CPUs and Arteris Ncore around the AMBA5 CHI.E standard. This validation work demonstrates to the ecosystem that they can be confident when choosing combinations of our IP to build their specific SoC solutions.”

Getting to Work – What Arteris Did as Part of the Arm Ecosystem

As part of the partnership agreement with Arm – announced in Fall 2022 – Arteris did get early access to the implementation views for some of the latest Cortex-A automotive enhanced IP, associated DynamIQ Shared Units (DSUs), and the Generic Interupt Controller (GIC). After aligning roadmaps for Ncore to support the latest CHI.E protocol to enable cache coherency, Arteris built, as part of their validation efforts, a four-cluster, eight-core system with four DSUs to test the aspects of cache coherency.

Example Setup for Arm – Arteris Cache Coherency Validation

At this time of the development processor, Ncore had already been verified using RTL simulation, connected to third-party verification IP for CHI-E, AXI, ACE, etc. In validation, the example system boots a Linux kernel and runs benchmark and validation applications to validate the transactions flowing through four 256-bit wide CHI-E ports @ 1GHz target frequency, mapped into emulation.

Besides the memory bandwidth observation for the Linux boot, the illustration below shows the bandwidth across the two coherence CHI-E ports. Once set up, Arteris runs 100s of tests in verification and validation (on emulation) to verify compatibility with CHI-E and the latest Armv9 Automotive Enhanced (AE) Products.

Illustration of validation results in emulation

The charts show the booting Linux v6.1.26 on am ARM Cortex-A Automotive Enhanced CPUs, with PMON configured to capture read/write/snoop bandwidth on the CHI-E interfaces and a PMON counter sample interval of 100us. RTL-based verification and emulation-based validation also use third-party waveform debug tools to analyze potential defects. With the combination of verification and validation in the system context, our mutual customers receive higher quality, pre-validated NoC implementations that reduce late surprises and finger-pointing when integrating multiple IP blocks, getting them to market faster.

Addressing Automotive Challenges

It is incredible how automotive electronics has evolved in just the last decade. Today, the design pattern requirements for System IP vary significantly. While lower-end automotive microcontrollers mostly require non-coherent interconnect, zonal controllers can be coherent or non-coherent depending on individual needs. Automotive vision designs tend to be largely non-coherent, and due to their more significant complexity, automotive cockpit, ADAS L2+, and more advanced autonomous vehicle designs almost always need a combination of coherent and non-coherent interconnects.

Diverse Coherency Needs in Automotive Electronics

Some of the highest-end building blocks in these designs can require large meshes that rival server-class designs. In contrast, others will need heterogeneous coherency. And that’s covering only the design choices. Now imagine developers adding varying safety and QoS constraints to their considerations.

That’s where Ncore Configurable Network-on-Chip IP Comes in!

With Ncore 3.6, announced at the same time as the most recent Arm automotive cores, users get the building blocks to build cache-coherent NoCs for highly scalable systems beyond meshes, i.e., supporting heterogeneous coherency, combined with a set of development tools to construct flexible networks and topologies with configurable snoop filters, extending to IO Coherency and supporting local and caches & system memory caches. Ncore is optimized to generate low-power optimized implementations with QoS support. Performance-wise, Ncore targets up to 1.4 GHz operation in 5nm technologies. Ncore has also received ISO2626 functional safety certification from Exida.
Focused on heterogeneous design targets, Ncore supports up to 16 coherent ports, up to 16 non-coherent or IO coherent ports, eight memory ports, eight peripheral ports, and eight directory ports. Users typically adopt it in combination with its non-coherent sibling, FlexNoC, which supports a wide range of network interfaces, including ACE-Lite, AXI, AHB, APB, OCP, and PIF.

Outlook

Ultimately, our validation work based on early access to Arm technology demonstrates to the ecosystem that they can be confident when choosing combinations of our IP to build their specific SoC solutions and that standards enable a choice of IP for various needs when developing automotive electronics.
And this is just the beginning!

As K. Charles Janac, President and CEO of Arteris said in the Arteris quote on the Silicon & Foundry Partner Page: