On 13 March 2024, Arm announced its latest and greatest processor cores targeted at automotive applications. These are the Arm Cortex-A720AE, formerly known as HunterAE, and the Arm Cortex-A520AE, formerly known as HayesAE. Both these cores implement the state-of-the-art Armv9 Instruction Set Architecture (ISA).

In addition to one or more Arm processor clusters, each comprised of multiple processor cores and a DynamIQ Shared Unit (DSU), integrating one or more cores with an L3 memory system, today’s system-on-chip (SoC) devices intended for automotive applications typically involve hundreds of other intellectual property (IP) functional blocks. These components include hardware accelerators, graphics processing units, neural processing units, on-chip memory, memory controllers for off-chip memory, and a wide variety of communications and peripheral functions.

Many of these IPs will be sourced from trusted third-party vendors. However, one or more proprietary IPs that differentiate an SoC from its competitors may be developed in-house, as well as the software for differentiation. All these IPs need to be connected to talk to each other at high speed with low latency and low power consumption. Also, this on-chip interconnect must use as few wires as possible to avoid routing congestion. The solution adopted by the vast majority of automotive SoC developers is a network-on-chip (NoC).

In the same way that Arm leads in providing the processor portion of automotive SoCs, Arteris is a leader in this market with respect to network-on-chip interconnects. In fact, per management and analyst estimates, more than 70% of today’s automotive ADAS SoCs shipped have an Arteris NoC inside.

To read the full article on Design & Reuse, click here.