Semiconductor Engineering: Aging Problems at 5nm and Below

by Madelyn Miller, On Jun 11, 2020

Aging Problems at 5 nm and Below 

June 11th, 2020 – By Brian Bailey

Semiconductor aging has moved from being a foundry issue to a user problem. As we get to 5nm and below, vectorless methodologies become too inaccurate. 

“The problem is that if somebody is doing their own chip, their own software in their own device, they have all the information they need to know, down to the transistor level, what that duty cycle is,” says Kurt Shuler, vice president of marketing at Arteris IP. “But if you are creating a chip that other people will create software for, or if you’re providing a whole SDK and they’re modifying it, then you don’t really know. Those chip vendors have to provide to their customers some means to do that analysis.”

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