Home » Newsroom » Blog » Semiconductor Engineering: Tech Talk – AI Training Chips Video

Semiconductor Engineering: Tech Talk – AI Training Chips Video

Jan 7, 2019
Kurt Shuler
< 1 min read

Kurt Shuler, VP of Marketing at Arteris IP, chat’s about how to speed up algorithms and improve performance:

Tech Talk Video: AI Training Chips

November 1, 2018 – By Ed Sperling

Ed Sperling interviews Kurt Shuler at Arteris IP headquarters about how to architect an AI training chip.

Arteris IP’s Kurt Shuler provides details about how different processing elements are used to accelerate training algorithms, and how to achieve improved performance .

To see the video on the SemiEngineering page, please click here:
https://semiengineering.com/ai-training-chips

See other SemiEngineering tech talk videos here.

Blogs

Latest Blogs

Blog

Electronic Design: Breaking Barriers in SoC Design with Smart NoC Automation

As SoCs grow in complexity, manual NoC generation is no longer practical. Discover how how automated NoC generation streamlines interconnect development to improve efficiency, scalability, and performance in advanced semiconductor designs.

Learn more about this

Blog

Semiconductor Engineering: Data Movement Is the Energy Bottleneck of Today’s SoCs

In today’s AI-focused semiconductor landscape, raw compute performance alone no longer defines the effectiveness of a system-on-chip (SoC). Learn more about how the right interconnect ensures that design teams are well-equipped to meet workload demands while achieving the performance and

Learn more about this

Blog

Unite.AI: Andy Nightingale, VP of Product Marketing at Arteris – Interview Series

Learn more about Andy Nightingale, VP of Product Marketing at Arteris. Throughout his 35-year career, Andy has held a range of roles, including engineering and product management positions at Arm, where he spent 23 years. In his current role, Andy

Learn more about this

Blog

Design & Reuse: Automating Hardware-Software Consistency in Complex SoCs

Magillem Registers automates hardware-software consistency, ensuring consistency, reducing errors, and accelerating development for efficient, innovative, and reliable designs.

Learn more about this

Blog

EDN: How NoC architecture solves MCU design challenges

Explore how today's NoC architectures solve MCU design challenges by optimizing timing closure, minimizing wire count, and reducing die area while supporting high-bandwidth, low-latency communication.

Learn more about this

Blog

Design News: The Hidden Technology Behind Faster, Smarter Silicon Chips

Engineering time can be significantly reduced thanks to the use of smart NoC IP technology like FlexGen smart NoC IP from Arteris. Learn more in the article.

Learn more about this

Semiconductor Engineering: Tech Talk – AI Training Chips Video

Tech Talk Video: AI Training Chips

Latest Blogs

Headquarters