Arteris Articles

Semiconductor Engineering: Interconnects Emerge As Key Concern For Performance

Kurt Shuler, Vice President of Marketing at Arteris IP is quoted in this new article in Semiconductor Engineering:

Interconnects Emerge As Key Concern For Performance

September 3rd, 2020 - By Ed Sperling

semiengineering-logo-2020Complexity, abundant options, and limits on tooling make this an increasingly challenging area. 

“On the AI side of things, the architecture is being determined by the capabilities of the interconnect,” said Kurt Shuler, vice president of marketing at Arteris IP. “It’s not just about the individual processing elements. It’s how do you get data between the processing elements and a whole bunch of local memories. In a lot of these AI chips, for power as well as latency and bandwidth, they want to limit as much as possible going off to DRAM, which means you’ve got to do the processing in situ within the chip. You can think of the interconnect as knobs and dials of what you’re capable of doing within these huge AI chips.”
 

To read the entire SemiEngineering article, please click here: https://semiengineering.com/interconnects-emerge-as-key-concern-for-performance/

 

Topics: SoC NoC NoC technology semiconductor engineering soc architecture DRAM AI chips noc interconnect IP market