Semiconductor Engineering: AI Chips: NoC Interconnect IP Solves Three Design Challenges

by Madelyn Miller, On Jan 14, 2019

AI Chips: NoC Interconnect IP Solves Three Design Challenges  

January 10th,  2019 – By Kurt Shuler

New network-on-chip (NoC) interconnect IP is now available for artificial intelligence (AI) systems-on-chip (SoC). Arteris IP launched the fourth generation of FlexNoC interconnect IP with a new AI package.

The new NoC technology benefits emerging AI chip architectures in three main ways: automatically generating regular topologies, effectively managing the data flows of large chips with long wires and enabling large on- and off-chip bandwidths.

To learn more, please visit the FlexNoC AI Package page; https://www.arteris.com/flexnoc-ai-package and the Resources page: https://www.arteris.com/resources

To see the entire on the SemiEngineering page, please click here:

https://semiengineering.com/ai-chips-noc-interconnect-ip-solves-three-design-challenges

 

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