Arteris Articles

Semiconductor Engineering: Shortening Network-on-Chip Development Schedules Using Physical Awareness

Frank Schirrmeister, VP Solutions and Business Development at Arteris IP, authored this Semiconductor Engineering article:

Shortening Network-on-Chip Development Schedules Using Physical Awareness

 January 5th, 2023 - By Frank Schirrmeister

Taking physical design into account as early as possible has been a consideration of chip development teams for quite some time. Still, in interactions with customers and partners, 2022 marked a sharp uptick in concerns about whether a design that may be functionally correct can also be implemented using physical implementation flows. Given the intricacies and complexity of network-on-chip (NoC) architectures and the dependencies on the size and placement of other IP blocks, they are susceptible to physical effects.

To read the full article on Semiconductor Engineering, click here.

Topics: SoC System-on-Chip NoC network-on-chip power Semiconductor Engineering security physical design design chip test