SemiWiki: On-Chip Networks at the Bleeding Edge of ML

by Kurt Shuler, On Dec 05, 2018

On-Chip Networks at the Bleeding Edge of ML 

November 29th,  2018 – By Bernard Murphy

I wrote a while back about some of the more exotic architectures for machine learning (ML), 2018-10-30-flexnoc-4-ai-4x8-meshespecially for neural net (NN) training in the data center but also in some edge applications. In less hairy applications, we’re used to seeing CPU-based NNs at the low end, GPUs most commonly (and most widely known) in data centers as the workhorse for training, and for the early incarnations of some mobile apps (mobile AR/MR for example), FPGAs in applications where architecture/performance becomes more important but power isn’t super-constrained, DSPs in applications pushing performance per watt harder and custom designs such as the Google TPU pushing even harder.

To read the entire article, please click here:
https://www.semiwiki.com/forum/content/7860-chip-networks-bleeding-edge-ml.html

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