Arteris Articles

Semiwiki: Taming Physical Closure Below 16nm

Arteris CEO Joins Bernard Murphy for this Semiwiki article.

Taming Physical Closure Below 16nm

 January 30th, 2023 - By Bernard Murphy

Atiq Raza, well known in the semiconductor industry, has observed that “there will be no simple chips below 16nm”. By which he meant that only complex and therefore high value SoCs justify the costs of deep submicron design. Getting to closure on PPA goals is getting harder for such designs, especially now at 7nm and 5nm. Place and route technologies and teams are not the problem – they are as capable as ever. The problem lies in increasingly strong coupling between architectural and logic design and physical implementation. Design/physical coupling at the block level is well understood and has been addressed through physical synthesis. However, below 16nm it is quite possible to design valid SoC architectures that are increasingly difficult to place and route, causing project delays or even SoC project cancellations due to missed market windows.

To read the full article on SemiWiki, click here.

Topics: SoC IP System-on-Chip NoC network-on-chip SemiWiki PPA AIP physical design Charlie Janac Arteris